隨著生醫、物聯網等產業近期迅速發展，無線通訊的接收、運算和輸出等眾多功能都要集中於同一晶片上，當製程越來越進步且功能越來越豐富，功耗和裝置本身的大小越來越重要。為了降低總功耗，讓系統處在待機或深度休眠模式會是比較有效率的方法，於必要時再喚醒系統執行任務，因此本研究將利用虛擬電阻(Pseudo-resistor)降低充電電流，設計一個全內建、面積小的低功耗低頻振盪器。
本研究使用台灣積體電路公司(TSMC)提供之0.18μm 1P6M Mixed-signal Standard CMOS製程，晶片總面積為0.968×0.838mm^2，並採用DIP 28 S/B進行封裝，晶片有四個版本的低頻振盪器，包含偏壓電路、充放電電路和比較邏輯電路，且不需要off-chip被動元件，各版本面積分別為0.083mm^2、0.0098mm^2、0.046mm^2、0.053mm^2，四個版本post-sim皆可輸出1Hz的方波，但量測結果不佳，最低頻率只有350Hz左右。

Low power consumption is important to wireless communication system. To reduce the power consumption, we can make the system stay in sleep-mode, and send a signal to wake it up and back to operation-mode. This thesis propose a fully built-in, low power consumption, and low frequency oscillator which meets the requirements. The output frequency of all versions are designed at 1Hz, and three of them are tunable frequency.
The proposed chip is fabricated by TSMC 0.18μm 1P6M mixed-signal standard CMOS process, and the chip area is 0.811 mm2. This chip includes four versions of low-frequency oscillator. The oscillator consists of three parts: bias circuit, charging-discharging circuit, and comparison logic circuit. Each version’s core area is 0.083mm^2, 0.0098mm^2, 0.046mm^2, and 0.053mm^2. The off-chip passive components are needless. The output frequency of all versions are 1Hz in the post-simulation. But the measurement result isn’t good, the lowest frequency is stable at around 355Hz under the same conditions.

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