在對矽晶片除錯過程中，硬體中斷點除錯技術可以讓使用者藉由停下電路時脈，透過測試架構(掃描鍊)擷取電路內部暫存器之狀態，當使用者需要設定下一個硬體中斷點以獲取更多電路內部的資訊時，電路時脈可被回復並繼續進行先前之運作，直到下一個硬體中斷點成立。此除錯技術亦被應用至以通訊協定進行資料交換的系統單晶片。然而先前相關技術的探討主要是以transaction作為除錯解析度，舉例來說，當硬體中斷點成立於transaction進行中時，電路時脈需等到transaction結束後才能被停下。當完成一個transaction需要很多時脈週期時，以transaction作為除錯解析度會太過於粗略，使得使用者無法觀察transaction進行中電路內部的運作狀態。在本篇論文當中，我們提出了一個針對系統單晶片且以時脈週期為除錯解析度的硬體中斷點矽除錯技術，稱其為通訊協定代理機制。此通訊協定代理機制可讓硬體中斷點除錯技術擁有時脈週期的除錯解析度。通訊協定代理機制可以處理發生電路時脈被中斷與被回復於未完成的transaction中時，所會出現的protocol violation與transaction invalidation等問題，如此一來可大大地增強矽除錯流程的彈性與效率。實驗結果說明，為了實現通訊協定代理機制所需付出的面積代價及效能代價非常少，甚至可以忽略不計；另外從通訊協定代理機制應用於對業界電路的除錯流程可看到，時脈週期的除錯解析度除了讓使用者可在硬體中斷點發生時立即觀察電路內狀態，相較於transaction的除錯解析度，透過時脈週期的除錯解析度可從電路中擷取的除錯資訊也有顯著的增加，大大地增進矽除錯的彈性與效率。

The breakpoint-based silicon debug approach allows users to stop normal operations of the circuits under debug (CUDs), extract the internal states of the CUDs for examination, and then resume normal system operations for further breakpoint setting. This approach has been applied to handshake-based SoCs. However, previously this approach is mainly at transaction-level granularity, i.e., the CUDs can be stopped only when a transaction is completed. The granulation at transaction level is often too coarse when a transaction requires a large number of cycles to complete. In this work, we present a novel debug mechanism, called the protocol agent, which allows the breakpoint-based debug technique to be applied at cycle-level granularity. The protocol agent is capable of dealing with the transaction invalidation and the protocol violation problems that may occur when a system is to be resumed from an incomplete transaction; thereby it can greatly enhance the flexibility and efficiency of the silicon debug process. Experimental results show that the area overhead of the protocol agent is quite low and the performance impact on the system is negligible. A case study with an industry design on Field Programmable Gate Array (FPGA) prototyping board validates the correctness, effectiveness and efficiency of the protocol agent mechanism on an SoC.

[1]Bart Vermeulen, “Functional Debug Techniques for Embedded Systems,” IEEE Design & Test of Computers, pp. 208-215, May-June 2008.
[2]K. Holdbrook, S. Joshi, S. Mitra, J. Petolino, R. Raman, and M. Wong. “microSPARCTM: A Case study of scan-based debug,” In Proc. IEEE Int’l Test Conference (ITC), 1994.
[3]Gert Jan van Rootselaar, Bart Vermeulen, “Silicon Debug: Scan Chains Alone Are Not Enough,” In Proc. IEEE Int’l Test Conference (ITC), 1999.
[4]Bart Vermeulen, Tom Waayers, Sandeep Kumar Goel, “Core-Based Scan Architecture for Silicon Debug,” In Proc. IEEE Int’l Test Conference (ITC), 2002.
[5]Bart Vermeulen, Sandeep Kumar Goel, “Design for Debug: Catching Design Errors in Digital Chips,” IEEE Design & Test of Computers, pp. 35-43, 2002.B. Vermeulen, Philips Res. Lab., Eindhoven, Netherlands Waayers, T., Goel, S.K., “Core-Based Scan Architecture for Silicon Debug,” Proc. IEEE Int’l Test Conf., Pages 638–647, 2002.
[6]Kees Goossens, Bart Vermeulen, Remco van Steeden, Martijn Bennebroek,” Transaction-Based Communication-Centric Debug,” In Proc. Int’l Symposium on Networks on Chip (NOCS), pp. 95-106, May 2007.
[7]Bart Vermeulen, Kees Goossens, “Interactive Debug of SoCs with Multiple Clocks,” IEEE Design & Test of Computers, vol. 60, no. 7, July 2011.
[8]Hyunbean Yi, Sungju Park and Sandip Kundu, “A Design-for-Debug(DfD) for Noc-based Soc Debugging via NoC,” ATS, pp. 289-294, Nov. 2008.
[9]Hyunbean Yi, Sungju Park and Sandip Kundu, “On-Chip Support for NoC-Based SoC Debugging,” IEEE Transactions on Circuits and Systems, vol. 57, no. 7, July 2010.
[10]Kuen-Jong Lee, Si-Yuan Liang, Alan Su, “A Low-Cost SOC Debug Platform Based on On-Chip Test Architectures,” Proc. SOC Conference, pp. 161~164, 2009.
[11]ARM, AMBA AHB Protocol Specification.
[12]ARM, AMBA AXI Protocol Specification.
[13]Fu-Ching Yang, Yi-Ting Lin, Chung-Fu Kao, Ing-Jer Huang, “An On-Chip AHB Tracer With Real-Time Compression and Dynamic Multiresolution Supports for SoC,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 19, no. 4, April 2011.
[14]Ehab Anis Daoud, Nicola Nicolici, “Real-Time Lossless Compression for Silicon Debug,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 9, September 2009.
[15]Ehab Anis Daoud, Nicola Nicolici, “On Using Lossy Compression for Repeatable Experiments during Silicon Debug,” IEEE Transactions on Computers, vol. 60, no. 7, July 2011.
[16]OCP International Partnership, Open Core Protocol Specification.
[17]OpenCores, Available: http://opencores.org/
[18]ARM, RealView ICE and RealView Trace User Guide, http://www.arm.com
[19]ARM, RVDS Toolchain, http://www.arm.com/zh/products/tools/software-tools/rvds/index.php
[20]SOCLE TECHNOLOGY CORP., SCDK-II, http://www.socle-tech.com/en/service_63.html