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研究生： 曾資育
Zeng, Zi-Yu
論文名稱： 高PSR 之低壓降線性穩壓器
A Low Dropout Linear Regulator with High Power Supply Rejection
指導教授： 蔡建弘
Tsai, Chien-Hung
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2008
畢業學年度： 96
語文別： 中文
論文頁數： 65
中文關鍵詞： 低壓線性穩壓器
外文關鍵詞： LDO
相關次數： 點閱：48  下載：17 
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    • 本論文提出一個具有高電源拒斥效能低壓降線性穩壓器電路並建立一個完整設計流程包括了低壓降線性穩壓器和帶差參考電壓兩種電路。藉由結合了電源漣波減法器和高通濾波器兩種技術來達到改善電源拒斥效能。本電路使用TSMC 0.35um CMOS 2-poly 4-metal 標準製程技術。在最大負載電流為100mA、輸入電壓3.3V 下模擬PSR 效能的結果為： 10K Hz 的電源拒斥為-73.2dB、
    100K Hz 的電源拒斥為-70.4dB、1M Hz 的電源拒斥為-39.2dB。所以本論文提出的低壓降線性穩壓器架構適用於前級切換式穩壓器的應用。總晶片面積為720×600μm2。

    A low dropout regulator (LDO) of high power supply rejection (PSR) over wideband frequency is presented in this thesis, and a systematic procedure including LDO and
    bandgap circuits is introduced. By combining supply ripple subtraction and high-pass filtering techniques, the proposed LDO’s PSR is improved. The proposed LDO
    implemented with a standard 0.35μm CMOS 2-poly 4-metal process technology. The simulation results at maximum load current of 100mA and input voltage of 3.3v show that
    the PSR of 10k, 100k and 1M are -73.2dB, -70.4dB and -39.2dB respectively. Therefore,it’s well suited for switching pre-regulator applications. The active area of this LDO is 720×600μm2.

    第一章 緒論..........................................................................................................................1 1.1 背景與動機............................................................................................................ 1 1.2 相關發展................................................................................................................ 3 1.3 論文架構簡介........................................................................................................ 4 第二章 基本的低壓降線性穩壓器......................................................................................6 2.1 基本的名詞與定義............................................................................................... 6 2.1.1 輸出電壓差(Dropout Voltage)...................................................................... 6 2.1.2 靜態電流(Quiescent Current) ....................................................................... 7 2.1.3 效率(Efficiency)............................................................................................ 8 2.1.4 線性調節率(Line Regulation) ...................................................................... 8 2.1.5 負載調節率(Load Regulation) ..................................................................... 9 2.1.6 電源拒斥(Power Supply Rejection) ............................................................. 9 2.1.7 輸出雜訊電壓(Output Noise Voltage) ....................................................... 12 2.1.8 功率損耗和接面溫度(Power Dissipation and Junction Temperature) ...... 12 2.1.9 輸出準確率(Output accuracy) .................................................................... 13 2.2 工作原理............................................................................................................. 14 2.3 低壓線性穩壓器的暫態與頻率響應................................................................. 15 2.3.1 頻率響應..................................................................................................... 15 2.3.2 暫態響應..................................................................................................... 18 2.4 保護電路............................................................................................................. 19 2.4.1 電池倒裝保護(Reverse Battery Protection) ............................................... 20 2.4.2 電流限制保護(Current-Limit Protection) .................................................. 21 第三章 PSR 改善之低降壓線性穩壓器...........................................................................22 3.1 簡介..................................................................................................................... 22 3.2 PSR 效能改善之LDO 架構比較....................................................................... 22 3.3 提出的高PSR 之LDO 架構............................................................................... 25 3.3.1 系統規格..................................................................................................... 26 3.3.2 系統交流小訊號模型與補償器設計......................................................... 29 3.4 電路設計與模擬................................................................................................. 31 3.4.1 控制迴路..................................................................................................... 31 3.4.2 高通濾波器................................................................................................. 34 3.5 帶差參考電路(bandgap voltage reference) ........................................................ 36 3.5.1 電路實現..................................................................................................... 37 3.5.2 設計流程與考量......................................................................................... 41 第四章 模擬結果與佈局....................................................................................................51 4.1 電路佈局............................................................................................................ 51 4.2 電路模擬結果..................................................................................................... 53 第五章 結論........................................................................................................................59 5.1 總結與貢獻......................................................................................................... 59 5.2 未來研究方向...................................................................................................... 59 參考文獻..............................................................................................................................60

    [1] TI, ”電池操作型可攜式應用的直流電源轉換,” 新電子科技雜誌, 2004 年6 月號
    [2] B. S. Lee, “Understanding the Terms and Definitions of LDO Voltage Regulators,”
    Application Report, Texas Instruments Inc., October 1999
    [3] V. Gupta and G.A. Rincon-Mora, "A 5mA 0.6um CMOS Miller-Compensated LDO
    Regulator with -27dB Worst Case Power Supply Rejection Using 60pF of On-Chip
    Capacitance," IEEE ISSCC, San Francisco, CA, pp.520-521,Feb. 2007.
    [4] C. Lee, and K. McClellan, “A Supply-Noise-Insensitive CMOS PLL With a Voltage
    Regulator Using DC–DC Capacitive Converter,” IEEE J. Solid-State Circuits,
    vol.36, no. 10, pp. 1453-1463, OCTOBER 2001.
    [5] S. K. Hoon, S. Chen. F. Maloberti, J. Chen, and B. Aravind, “A low noise, high power
    supply rejection low dropout regulator for wireless system-on-chip applications,”
    IEEE Custom Integrated Circuits Conf, pp. 754- 757, Sept. 2005.
    [6] J. Chen, and X. Xi, “Low dropout voltage regulator with improved power supply
    rejection ratio,” U.S. Patent 6 541 946 B1, Apr. 1, 2003
    [7] V. Gupta and G. A. Rincon-Mora, “Analysis and design of monolithic, high PSR,
    linear regulators for SOC applications,” in Proc.IEEE SOC Conf, pp.311-315, Santa
    Clara, California, 2004.
    [8] Bang S. Lee. “Technical Review of Low Dropout Voltage Regulator Operation and
    Performance,” Application Report, Texas Instruments Inc., October 1999
    [9] Gabriel Alfonso Rincon-Mora, Current Efficient, Low Voltage, Low Drop-Out
    Regulators, Ph.D Thesis, Georgia Institute of Technology, November 1996.
    [10] M. Tuthill, “A switched-current, switched-capacitor temperature sensor in 0.6μm
    CMOS,” IEEE Journal of Solid-State Circuits, vol.33,no. 7, pp. 1117- 1122, July
    1998.
    [11] W. Oh, B. Bakkaloglu,“A CMOS LOW-NOISE, LOW-DROPOUT REGULATOR
    FOR TRANSCEIVER SOC SUPPLY MANAGEMENT,” IEEE SOC Conference,
    PP.7-10, Sept 2006.
    [12] Kieran O’Malley, “Linear Regulator Protection Circuitry”, Application Note,On
    Semiconductor Inc., May 1990.
    [13] James Wong, “ A Low-Noise Low Dropout Regulator for Portable Equipment,”
    Powerconversion and Intell. Motion, pp. 38–43, May 1990.
    [14] M. S. J. Steyaert and W. M. C. Sansen, “Power Supply Rejection Ratio in Operational
    Transconductance Amplifiers”, IEEE J. Solid-Stage Circuits, vol.37, pp.1077-1084,
    Sep. 1990.
    61
    [15] L. Shen, Z. Yan “Design of High-Performance Voltage Regulators Based on
    Frequency-Dependent Feedback Factor, ”IEEE International Symposium on Circuits
    and Systems, pp. 3828-3831 , May 2007
    [16] K. E. Kuijk, “A precision reference voltage source,” IEEE Journal of Solid-State
    Circuits, vol. SC-8, pp. 222–226, June 1973.
    [17] Razavi, Design of Analog CMOS Integrated Circuit, McGraw-Hill, 2001.
    [18] Philip MoK, “Design of Power Management IC- Voltage Reference, Low-Dropout
    Regulator and Switching Regulator,” 2005 混合訊號式積體電路設計專題研討會.
    [19] X. Fan, C. Mishra, “Single Miller capacitor frequency compensation technique for
    low-power multistage amplifiers,” IEEE Journal of Solid-State Circuits, VOL.40,
    NO. 3, pp.584-592, MARCH 2005.
    [20] Sai Kit Lau, Member, IEEE, Philip K. T. Mok, Senior Member, IEEE, “A
    Low-Dropout Regulator for SoCWith Q-Reduction,”IEEE journal of solid-state
    circuits, vol.42, no. 3, pp. 658-664, March 2007.
    [21] Tsz Yin Man, Student Member, IEEE, Philip K. T. Mok, Senior Member, IEEE, “A
    High Slew-Rate Push-Pull Output Amplifier for Low-Quiescent Current Low-
    Dropout Regulators With Transient-Response Improvement,” IEEE Transactions on
    Circuits and Systems II, vol.54, no. 9, pp. 755-759, Sept. 2007.

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