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研究生： 張君豪
Chang, Chun-Hao
論文名稱： 具步階位移背景誤差校正之8位元2GS/s快閃類比數位轉換器
An 8-bit 2GS/s Flash ADC with Step-Shifted Background Offset Calibration
指導教授： 郭泰豪
Kuo, Tai-Haur
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2014
畢業學年度： 102
語文別： 英文
論文頁數： 90
中文關鍵詞： 比較器 、偏移誤差校正 、背景式偏移誤差校正 、快閃式類比數位轉換器
外文關鍵詞： Comparator, offset calibration, background calibration, flash analog-to-digital converter (ADC)
相關次數： 點閱：128  下載：8 
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    • 本論文提出一個數位背景式偏移誤差校正技術，用以消除快閃式類比數位轉換器中比較器之偏移誤差。所提出的具步階位移背景式偏移誤差校正技術可以不中斷原本類比數位轉換器的操作並校正偏移誤差。本技術利用開關使得比較器的參考電壓產生一個最小值位元的步階位移。輸入訊號因為偏移誤差在不同步階位移下產生相同的溫度計編碼之機率不同，根據不同步階位移狀況輸出的溫度計編碼可以偵測比較器偏移誤差的極性，進而校正比較器之偏移誤差。此外本論文分析了對於數位偏移誤差矯正技術產的雜訊。
    本論文實現一具步階位移背景式偏移誤差校正技術之八位元每秒二十億次取樣快閃式類比數位轉換器，此實現是採用TSMC 90奈米，1P9M互補型金氧半導體製程。量測結果顯示，在2GHz的取樣速率以及5MHz的輸入頻率下，尚未開啟偏移誤差校正前SNDR為19.0dB，經過偏移誤差矯正後有32.4dB之SNDR動態表現。在1V電壓下，整個晶片不包含輸出緩衝器共消耗104mW之功率，FOM於輸入低頻時達到1.29pJ/conversion-step。

    A digital background offset calibration technique is proposed in this thesis. The proposed scheme, named step-shifted background calibration (SSBC), was developed for trimming the input-referred offset voltage of the comparators in a flash ADC without interrupting the ADC’s normal operation. By using reference voltage switches, the comparator reference voltage is step-shifted by one VLSB. For an input signal, the probability of the same thermometer code output would not be the same for different step-shifts; nevertheless, the polarity of the comparator offset voltage can be detected from the thermometer code output after different step-shifts. Noise analyses of digital calibration techniques are also presented in this thesis.
    An 8-bit 2GS/s flash ADC with step-shifted background calibration is implemented by TSMC 90nm 1P9M CMOS process. Before calibration, the measurement results show that the SNDR is 19.0dB with 5MHz input frequency at a 2GHz sampling rate. After calibration, measured SNDR is 32.4dB. The power consumption is 104mW from a 1 V supply for which output buffers are not included. The FOM of this ADC is 1.29pJ/conversion-step at low frequency input.

    Chapter1 Introduction 1 1.1 Motivation 1 1.2 Organization 3 Chapter2 Error Analyses of Flash ADC 5 2.1 Quantization error 5 2.2 Noise 6 2.3 Offset Mismatch 10 2.3.1 Reference offset 11 2.3.2 Comparator offset 14 2.4 Clock Jitter 17 2.5 Signal Dependent Delay Error 18 2.6 Metastability 22 Chapter3 Proposed Offset Calibration Technique 25 3.1 Algorithm of SSBC 25 3.2 Comparator-Shifted Background Calibration 29 3.3 Reference-Ladder and Comparator Shifted Background Calibration 33 3.4 Cascade Step-Shifted Background Calibration 35 Chapter4 ADC Digital Calibration Noise Analyses 42 4.1 Trimming Resolution Noise 43 4.2 Balancing Bouncing Noise 45 4.3 Statistical Error Noise 47 4.4 Noise Analyses of SSBC 51 4.4.1 DNL analysis of SSBC 52 4.4.2 INL analysis of SSBC 53 Chapter5 Circuit Design of Flash ADC 57 5.1 The Architecture of Proposed ADC 57 5.2 Reference Ladder Consideration 59 5.2.1 Mismatch of Resistor Ladder 59 5.2.2 Input Feed-Through of Resistor Ladder 60 5.3 Track and Hold Circuit 61 5.4 Comparator Circuit Design 62 5.4.1 Circuit Topology and Consideration 63 5.4.2 Preamplifier Circuit 64 5.4.3 Latch Comparator Circuit 64 5.5 Digital Calibration Circuit 65 5.5.1 SSBC Parameter Design 65 5.5.2 Phase Generator 66 5.5.3 Additional Offset-Adjusting Circuit 68 5.5.4 Offset calibration DAC 69 5.6 Digital Encoder 71 5.7 Timing Generator Circuit 71 Chapter6 Layout and Measurement Results 73 6.1 Floor Plan and Layout 73 6.2 Simulation result 75 6.3 Measurement Setup 77 6.4 PCB Design Consideration 78 6.4.1 Transmission line effect 78 6.4.2 Parasitics 78 6.4.3 PCB fabrication 80 6.5 Measurement result 82 Chapter7 Conclusion and Future Work 87 Reference 88

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