| 研究生: |
蘇俊銘 Su, Jun-Ming |
|---|---|
| 論文名稱: |
H.264適應性可變長度解碼器之設計 Design of CAVLC Decoder for H.264/AVC Video Coding |
| 指導教授: |
賴源泰
Lai, Yen-Tai |
| 學位類別: |
碩士 Master |
| 系所名稱: |
電機資訊學院 - 電機工程學系 Department of Electrical Engineering |
| 論文出版年: | 2013 |
| 畢業學年度: | 101 |
| 語文別: | 英文 |
| 論文頁數: | 61 |
| 中文關鍵詞: | H.264/AVC 、熵編碼 、內容適應性可變長度編碼 |
| 外文關鍵詞: | H.264/AVC, Entropy coding, CAVLC |
| 相關次數: | 點閱:122 下載:0 |
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近年來,許多影像壓縮編碼標準相繼被提出,而H.264/AVC是最熱門的影像壓縮編碼標準。為了要擁有更高的壓縮效率,H.264/AVC的熵編碼(Entropy Coding)部分採用內容適應性可變長度編碼(context-based adaptive variable length coding, CAVLC) ,適應性可變長度編碼是一種無失真的壓縮方式,用來移除統計上的冗餘位元提高編碼效率。
適應性可變長度編碼在進行解碼的過程中,需要大量的記憶體存取,進行的查表動作,這會增加功率消耗也會需要較高的硬體成本。
本篇論文主要研究CAVLC解碼器部分,研究如何減少硬體成本以及降低功率消耗的方法。我們分析CAVLC相關的字碼表建立其規則,在Coeff_token及Run_before兩個部分,使用一個計數器找出第一個不為零係數前面零的個數結合整數算術解碼方式取代傳統的查表法。在Total_zeros部分,我們將碼表分組後再改良傳統的查表法。最後根據實驗結果,我們所設計的電路與傳統的架構相比,平均功率消耗大約可以降低32%到38%,在合成結果中顯示,電路只需要6.78K個邏輯閘。
Several video compression coding standards have been proposed in recent years. H.264/AVC is one of the most popular formats for video compression coding. To enhance compression efficiency, context-based adaptive variable length coding (CAVLC) is used in the entropy coding of H.264/AVC. The CAVLC approach is adopted for lossless compression method, and is used to remove statistical redundancy and improve coding efficiency.
A large amount of memory accesses are required for the CAVLC decoding process. This increases power consumption and necessitates the use of costly hardware.
This paper mainly studies the CAVLC decoder. We investigated methods of reducing the hardware costs and power consumption. We analyzed CAVLC codeword table to establish the rules of the CAVLC decoding process, and adopted a zero counter to calculate the total number of zeros preceding the first non-zero coefficient. This method was combined with an integer arithmetic operation, which replaced the traditional table lookup method in two parts: Coeff_token and Run_before. We classify a codeword table to improve the traditional table lookup method in the Total_zeros part.
According to our simulation, the proposed design saves 32% to 38% in power consumption, compared with the original design. The synthesis result shows that the gate count was 6.78K.
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校內:2023-07-01公開