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研究生：	林韋光 Lin, Wei-guang
論文名稱：	用於H.264快速內框預測之新方向偵測法與其VLSI設計 A Novel Direction Detection Algorithm and Its VLSI Design for Fast H.264 Intra Prediction
指導教授：	王駿發 Wang, Jhing-Fa
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2007
畢業學年度：	95
語文別：	英文
論文頁數：	67
中文關鍵詞：	內框預測、新方向偵測法
外文關鍵詞：	Direction detection, Intra prediction, H.264
相關次數：	點閱：62 下載：2
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H.264/MPEG-4 Part 10 AVC是新一代的視訊壓縮標準，由ITU-T和ISO/IEC兩大國際組織共同制定與命名。H.264/AVC的主要目標是超越先前的壓縮標準，並達到最佳的壓縮效能。因此，H.264採用計算複雜度極高的ROD (rate distortion optimization) 技術，檢測所有的預測模式，以找出最適合的預測模式。在4x4區塊中，Intra Prediction共有九種預測模式，而在16x16與8x8區塊中，各有4種預測模式。雖然全域搜尋的方式可以提高編碼效能，但是龐大的計算量卻使得壓縮速度緩慢，且不容易實現。
在本論文中，我們提出一套新式且高效率、高可靠度的方向偵測法。本論文提出的演算法，有效率地預測區塊內容的主要方向，減少預測模式，明顯降低了RDO的運算量。實驗結果顯示，本論文提出的方法可以降低60%的編碼時間，並僅減低些許的效能。硬體設計方面，此快速預測模式的電路，由0.18 m CMOS 製程實現，其面積核心為0.12x0.12 mm2。此設計為三級的pipeline架構，最大操作速度為173MHz，可以編碼30 fps的即時影像到達Level 5.0。由於低成本、高速度與低功率等議題在SOC設計中，佔有越來越重要的地位。因此，本作品不僅能廣泛用於及時系統，亦能實現於編碼器中，在軟體與硬體的表現，都是相當吸引人的矽智財。

The H.264/MPEG-4 Part 10 Advanced Video Coding (AVC) is a latest coding standard that is developed by Joint Video Team of ITU-T VCEG and ISO/IEC MPEG. The goal of H.264/AVC is to achieve better coding efficiency than the existing video coding standards. Hence, H.264 employs the computationally extensive rate distortion optimization (RDO) technique to examine exhaustively all possible modes for finding the best mode. There are nine prediction modes in intra 4x4 prediction, and four modes in intra 16x16 and 8x8 predictions. Although full search strategy achieves high coding performance, but large computation complexity makes it timing-wasting and unpractical.
In this thesis, we propose a novel and efficient but reliable direction detection algorithm. The proposed methods effectively estimate the major direction inside the block to narrow down the predictive modes to reduce the RDO computation. Experimental results show that the proposed methods can reduce the encoding time by about 60% with negligible loss of coding performance. For the hardware architecture design, a fast mode decision VLSI circuit for intra prediction with the silicon core size of 0.12x0.12 mm2 at 0.18 m CMOS technology is implemented. A three-stage pipelined architecture operated at 173 MHz can encode 30 fps real-time videos up to Level 5. Owing to the low cost, high speed and low power issues in SOC design, our work would be an attractive hardware or software intellectual property (IP) for real-time application and H.264 encoder realization.

Contents
摘要.......................................3
Abstract...................................4
誌謝.......................................6
Contents...................................7
Table List................................10
Figure List...............................11
CHAPTER 1  INTRODUCTION...................14
1.1	Background.......................14
1.2	Motivation.......................14
CHAPTER 2	OVERVIEW OF INTRA PREDICTION IN H.264/AVC.....17
2.1	Modes Decision for Intra Prediction...........17
2.1.1	4x4 Luma Prediction Modes........17 
2.1.2	16x16 Luma Prediction Modes......19
2.1.3	8x8 Chroma Prediction Modes......19
2.2	Mode Decision....................20
CHAPTER 3	PREVIOUS WORKS...................23
3.1	Introduction to MPEG-7 Edge Histogram
         Descriptor.............23
3.2	Dominant Edge Strength Algorithm....24
3.2.1	Preprocessing of Image Block........24
3.2.2	Edge Strength Calculation...........25
3.2.3	Dominant Edge Decision..............26
3.2.4	Fast Mode Decision of Luma 4x4......27
3.2.5	Fast Mode Decision of Luma 16x16 and 
         Chroma 8x8........28

CHAPTER 4	OUR PROPOSED DIRECTION DETECTION ALGORITHM.....29
4.1	The Motivation to Proposed A Novel 
         Algorithm................29
4.2	Subblock-based Direction Detection 
         Algorithm (SBDD)............30
4.2.1  Preprocessing of Image Block.......30
4.2.2  Direction Detection Computation....30
4.2.3  Fast Modes Decision with Dominant 
       Direction Strength.........33
4.2.4  Subblock-based DD Algorithm for Luma 16x16 
       and Chroma 8x8............34
4.3    Pixel-based Direction Detection 
       Algorithm (PBDD)..........37
4.3.1  Analysis of Difference Among Pixels..37
4.3.2  Direction Detection Computation......38
4.3.3  Fast Mode Decision with Dominant 
       Direction Strength...............39
4.3.4  Pixel-based DD Algorithm for Luma 4x4 and 
       Chroma 8x8.........................40
4.4    Experimental Results...............42
4.4.1  Testing Method and Environment.....42
4.4.2  Performance Comparison with Previous Works......43
CHAPTER 5	ARCHITECTURE DESIGN FOR PROPOSED 
        SBDD ALGORITHM....................48
5.1     System Overview of Intra Coder....48
5.2     Architecture Design for DD Preprocessor.....49
5.2.1   Zigzag Converter Unit.............50
5.2.2   DD Core Unit......................52
5.2.3   DD FSM Unit.......................57
5.2.4   Simulation Waveform and Synthesis Results...58
5.3     Implementation Results............61
CHAPTER 6	  CONCLUSIONS....................64
REFERENCES................................65
                                    

Reference
[1]Information Technology—Coding of Audio-Visual Objects—Part 10: Advanced Video Coding, Final Draft International Standard, ISO/IEC FDIS 14496-10, March 2005.
[2]“Report of the formal verification tests on AVC (ISO/IEC 14496-10 ITU-T Rec.H.264),” MPEG2003/N6231, Dec. 2003.
[3]W. W. Huang, B. Y. Hsieh, T. C. Chen, and L. G. Chen, “Analysis, fast algorithm, and VLSI architecture design for H.264/AVC intra frame coder,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 15, no. 3, pp.378–401, Mar. 2005.
[4]F. Pan, X. Lin, S. Rahardja, K. P. Lim, Z. G. Li, D. Wu, and S. Wu, “Fast mode decision algorithm for intraprediction in H.264/AVC video coding,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 15, no. 7, pp. 813-822, July 2005.
[5]J. C. Wang, J. F. Wang, J. F. Yang and J. T. Chen, “A Fast Mode Decision Algorithm and Its VLSI Design for H.264/AVC Intra Prediction,” IEEE Transactions on Circuits and Systems for Video Technology, 2007. (Accepted).
[6]Y. W. Huang, B. Y. Hsieh, T. C. Chen, and L. G. Chen, “Analysis, fast algorithm, and VLSI architecture design for H.264/AVC intra frame coder,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 15, no. 3, pp.378–401, Mar. 2005.
[7]C. W. Ku, C. C. Cheng, G. S. Yu, M. C. Tsai, and T. S. Chang, A high-definition H.264/AVC intra-frame codec IP for digital video and still camera applications, IEEE Transactions on Circuits and Systems for Video Technology, vol. 16, no. 8, pp. 917-928, August 2006.
[8]T. Wiegand, G. J. Sullivan, G. Bjontegaard, and A. Luthra, “Overview of the H.264/AVC video coding standard,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 13, no. 7, pp.560-576, July. 2003.
[9]“Draft ITU-T recommendation and final draft international standard of joint video specification (ITU-T Rec. H.264/ISO/IEC 14 496-10 AVC,” in Joint Video Team (JVT) of ISO/IEC MPEG and ITU-T VCEG, JVTG050, 2003.
[10]Huang, B. Y. Hsieh, T. C. Chen, and L. G. Chen, “Analysis, fast algorithm, and VLSI architecture design for H.264/AVC intra frame coder,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 15, no. 3, pp. 378-401, March 2005.
[11]Joint Video Team Reference Software JM 10.0 :
http://iphome.hhi.de/suehring/tml/download/
[12]Bojun Meng, Oscar C. Au, Chi-Wah Wong, Hong-Kwai Lam, "Efficient intra-prediction algorithm in H.264," ICIP (3) 2003, 837-840
[13]C. C. Cheng, T. S. Chang, “Fast Three Step Intra Prediction Algorithm for 4x4 blocks in H.264,” ISCAS 2005, vol. 2, pp. 1509 - 1512.
[14]C. H. Tseng, H. M. Wang, J. F. Yang, “Improved and Fast Algorithms for Intra 4x4 Mode Decision in H.264/AVC,” ISCAS 2005, vol.3, pp. 2128 - 2131.
[15]F. Fu, X. Lin, and L. Xu, “Fast Intra Prediction Algorithm in H.264 AVC,” ICSP 2004, vol. 2, pp. 1191 - 1194.
[16]Bojun Meng, Oscar C. Au, “Fast Intra-Prediction Mode Selection for 4x4 Blocks in H.264,” ICASSP 2003, vol. 3, pp. III - 389 - 92.
[17]C. S. Won, D. K. Park, and S. J. Park, “Efficient use of MPEG-7 edge histogram descriptor,” ETRI Journal, vol. 24, no. 1, pp. 23-30, February 2002.
[18]MPEG7 Visual Experimentation Model (XM), Version 10.0, ISO/IEC/JTC1/SC29/WG11, Doc. N4063, Mar. 2001.

校內：2008-07-11公開
校外：2008-07-11公開

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