數位像素感測器這個名詞在近五、六年來迅速崛起，其高速操作之優點符合未來像素陣列擴大且畫面更新率加快之趨勢，並且除了速度上之優勢，在雜訊上的消除以及動態範圍的提升也具有相當優異的表現，目前有越來越多的學者正朝這個方向研究。然而，龐大的像素電路卻也隱藏多問題值得探討。當像素電路變大時，光二極體之周邊電路運作可能會帶來更多的雜訊。因此，本論文探討像素電路操作時，對光二極體以及像素輸出之影響。
論文中以台灣積體電路公司0.18μm 1P6M 1.8V混合訊號製程，實做了一個具測試像素電路雜訊能力之數位像素感測器，晶片面積1.253×1.253 mm²，像素陣列大小為60×60。像素中類比數位轉換器解析度為八位元，轉換時間為10.24μs，整個晶片可達到最快畫面更新率為12207 frames/s。除數位像素感測器之主電路架構外，在像素電路中額外加入主動式像素感測器來直接讀取光二極體之類比訊號，並交由後級之相關二次取樣電路消除固定圖像雜訊。晶片中可分為類比與數位兩部分，彼此可獨立運作，藉由在不同頻率下操作數位影像感測電路，可觀察類比輸出之結果，探討並分析像素電路操作時，對光二極體的影響與干擾情形。

Digital pixel sensor(DPS) has grown quickly in recent five or six years. Beside the advantage of high speed operation, it shows excellent performance on noise elimination and dynamic range promotion. More and more scholars devote themselves to this area of DPS. However, the large pixel circuits of DPS also bring some problems. When more and more transistors are implemented into pixel circuit, the photodiodes may influence by the noise induced by transistors’ operation much more seriously. For this reason, my topic is studying on the effect induced by pixel circuits upon pixel outputs and photodiodes.
A DPS chip with noise testing capability is fabricated in TSMC 0.18μm 1P6M 1.8V mixed-mode process. Chip occupies the area of 1.253×1.253 mm² and pixel array is 60×60. Pixel level ADC’s resolution and conversion time are individual 8-bits and 10.24μs. The maximum frame rate the DPS chip can achieve is 12207 frames/s. Except DPS circuits, the active pixel sensor(APS) circuits are added in pixels to sample the photodiodes’ voltage directly. Then the analog signals are sampled by CDS circuits and column-to-column FPN is eliminated. This two parts of digital and analog work independently, hence the analog outputs can be observed under different operating frequency of DPS circuits. By measuring the analog output results obtained under different testing, the intensity of interference to DPS’s photodiodes will be detected and analyzing when pixel circuits are working.

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