在工業界的測試中掃描鏈設計被廣泛地使用，而使用掃描測試的成本大多源至於昂貴的外部測試機台，因此可以減少使用測試機台成本的自我測試(Build-In-Self-Test)變成一個相當具有吸引力的測試方法。然而，自我測試技術必須承擔亂數測試(random test)所造成長測試時間或是測試向量產生器(pattern generator) 的龐大電路面積。此篇論文提出一個新穎的測試架構結合了掃描測試與自我測試兩者的優點，此測試架構包含一個藉由掃描鏈儲存壓縮後的測試資料的儲存結構，由修改內部掃描鏈中掃描單元之間的連接達到儲存測試資料的目的，被儲存的測試資料可以經由晶片內測試控制器與測試解壓縮器讀取、重組並解壓縮成測試所需的決定性向量(deterministic pattern)，此論文並提出了一套可精確修改掃描鏈與接收測試資料的公式。此外，這個測試架構中的晶片內測試控制器可以自動產生配合測試流程的控制訊號，藉此大幅度降低或甚至去除測試機台需求與相對應的測試成本。實驗結果顯示，此測試架構僅需要相當小的面積，在一個8個核心的多核心電路, OpenSPARC T2，此測試平台只需要增加2.96%的硬體面積。

Scan-based design is widely used in industry. The test cost of scan-based design largely lies on the expensive, external ATE. Built-in self-test (BIST) is a test alternative that allows to reduce the cost of ATE. However, the BIST technology may suffer from long random pattern application time or large hardware overhead. This work proposes a novel test architecture that combines the advantages of both scan-based design and BIST architecture. The main idea is to store compressed test data in a novel scan chain structure such that the stored data can be extracted, reconstructed, reconfigured and decompressed into required deterministic patterns using an on-chip test controller. The storing of test data is achieved by modifying the connections between scan cells. Techniques to correctly extract test data from modified scan cells and to deliver test patterns to modified scan cells are presented. The on-chip test controller can automatically generate all required control signals for the whole test procedure. This significantly reduces the requirements on the external ATE. The test architecture provides full test coverage and incurs only a low area overhead. Experimental results show that the area overhead of the proposed on-chip self-test architecture is about 2.96% for the 8-core processor OpenSPARC T2

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