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研究生：	謝信男 Hsieh, Hsin-Nan
論文名稱：	毋須參考訊號之多重解析度抖動測試電路設計 Design of Multi-resolution Jitter Measurement Circuit without Reference Clock
指導教授：	謝明得 Shieh, Ming-Der
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2005
畢業學年度：	93
語文別：	英文
論文頁數：	66
中文關鍵詞：	多重解析度、自我參考訊號、抖動
外文關鍵詞：	jitter, multi-resolution, self-reference
相關次數：	點閱：111 下載：1
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　　隨著半導體製程的進步，積體電路發展已朝向系統整合方式發展，當許多的系統整合在一個晶片中，各電路的時序的掌控必須是要很準確，要是產生時脈歪曲就可能造成電路動作錯誤。所以在系統中，時脈訊號關係整個電路的效能，而鎖相迴路電路就為一個重要時脈訊號建構單元，其因為伴隨著製程的進步其操作速度也相對的提升也使的鎖相迴路電路的測試變的相當困難。
　　一般在量測時脈抖動時，通常需要透過外部昂貴的測試機台來完成，所以本論文提出一個可以內建在晶片中來做時脈抖動測量的電路，主要電路架構是採用VDL的方式且具有多重解析度的選擇以方便量測不同的時脈抖動來源有不同的抖動大小，此外使用毋須參考訊號的量測技術來完成整個測量電路，而測量到的時脈抖動數值會在晶片內部轉換成數位訊號在傳送出來做分析。
在本論文設計電路的操作輸入訊號定為100MHz，在微調解析度(30ps)下，可測量的範圍為1.68ns，而在粗調解析度(250ps)下，最大可測量範圍為5ns。電路設計模擬採用TSMC 0.35um 2P4M製程技術實現。

　As the technology scales to subtle feature sizes, the integration of more heterogeneous components into a System-On-a-Chip becomes inevitable. To guarantee correct operation of a system, because the clock skew will affect the performance of the system. In many practical applications, the Phase-Locked Loop (PLL) is recognized as one of the important components for clock recovery. As the system operates at higher and higher frequency, factors like clock jitter become crucial in PLLs.
　Conventionally, jitter is measured by using externally expensive Automatic Test Equipment (ATE). In this thesis, we propose an on-chip circuit to measure the jitter. The measurement circuit is based on the VDL architecture and it possesses the multi-resolution function, which can be used to measure different jitter quantity resulted from different jitter sources. Moreover, the self-referenced signal technique is adopted in the measurement circuit. The jitter value is translated to digital signal by the on-chip measurement circuit for output analysis. The operating frequency of the measurement circuit in this thesis is 100MHz with the measurement range being 1.68ns in fine-tune procedure (30ps) and 5ns in coarse-tune procedure (250ps). The measurement circuit is simulated using the TSMC 0.35um 2P4M technology.

Chapter 1 Introduction .................................................................................................1
1 Motivation .............................................................................................................1
2 Organization ..........................................................................................................3
Chapter 2 Previous Works ............................................................................................4
1 Jitter Definition......................................................................................................4
1.1 Period Jitter: JPER........................................................................................4
1.2 Cycle-to-cycle Jitter: JCC............................................................................6
1.3 Long-term Jitter: JLong.................................................................................7
1.4 Summary ....................................................................................................8
2 Sources of Jitter .....................................................................................................9
3 Jitter Separation ...................................................................................................12
3.1 Jitter Statistics ..........................................................................................12
3.2 Jitter Histogram........................................................................................13
3.3 Jitter Separation Motivation .....................................................................14
3.4 The Jitter Model .......................................................................................14
Chapter 3 Jitter Test Techniques..............................................................................22
1 Equipment Based Technique ...............................................................................22
2 On-chip Measurement Technique........................................................................23
Chapter 4 Proposed Jitter Measurement Circuit .......................................................28
1 The Self-Referenced Signal Technique ...............................................................28
2 Measurement Circuit Architecture.......................................................................30
3 Measurement Procedure ......................................................................................31
4 Design Sub-Circuit of Measurement Circuit .......................................................35
4.1 Multi-Resolution Block............................................................................35
4.2 Long Delay Cell .......................................................................................37
4.3 Fine Tune Delay Cell................................................................................40
4.4 Phase Detector..........................................................................................41
Chapter 5 Calibration and Simulation Result............................................................43
1 Calibration ...........................................................................................................43
1.1 The VDL measurement architecture.........................................................45
1.2 The vernier oscillator measurement architecture .....................................47
1.3 The quantization of measurement circuit .................................................48
2 Simulation Results...............................................................................................50
3 Measurement Time and Range ............................................................................53
Chapter 6 Conclusion and Future Work ....................................................................58
1 Conclusion...........................................................................................................58
2 Future work..........................................................................................................58
Appendix......................................................................................................................59
References....................................................................................................................64
                                    

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校內：2007-07-29公開
校外：2007-07-29公開

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