由於電子系統的複雜性與日劇增且深次微米的技術日益精進，近年來越來越多的功能整合在一個單晶片中 ( SoC ) 。因而在設計中結合數位和類比功能的晶片也增多了。但是使用混合信號設計所應用電路的發展對於測試而言是一種大挑戰而且越來越困難，因為測試此種晶片是十分昂貴且費時的。
在本文中，首先，我們設計一使用無損耗離散積分-梯狀結構之四階和差調變器 (4th-order SDM with LDI-ladder structure) 並結合一個傳統的數位振盪電路 (Digital Resonator) 來產生正弦波。其次，我們結合數位振盪電路和多位元和差調變器的架構提出一測試方式，其主要想法是藉由觀察系統環路上頻率和振幅偏差，由偏差值決定待測物的好壞。
我們在 MATLAB/SIMULINK中模擬整個系統，並且模擬結果顯示此種測驗方式能夠有效率地偵測出類比數位轉換器的徧差。

Due to the increasing complexity of electronic systems and the capabilities of deep sub-micron technologies, more and more system functionality has been integrated in a single chip (SoC) in recent years. Consequently there is an increasing number of chips that combine digital and analogue functions in all IC designs. However, this trend brings big challenge in the realm of testing since testing mixed-signal circuits is often both expensive and time consuming.
In this thesis, we first design a 4th-order SDM with LDI-ladder structure which is combined with a traditional digital resonator to generate a sinusoidal wave. Secondly, we propose a test methodology based on a configurable test loop which consists of the digital resonator, Multi-bit SDM and CUT, The basic idea is to determine whether a CUT is a good or faulty one by observing the deviation of the oscillating frequency and amplitude of the whole test loop.
We simulate the whole system by using MATLAB/SIMULINK. The simulation results show that the proposed test method can efficient to detect deviation of the ADCs.

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