低功率類比數位轉換器對於許多應用為核心電路，尤其對於可攜帶性的裝置。本論文呈現使用於主動式影像感測器的獨立式逐次漸進式類比數位轉換器，此實驗性晶片的規格以320×240的感測矩陣(QVGA)以及每秒12頁畫面更新率為目標規格。使用TSMC 0.35μm混合式訊號CMOS製程，含兩層多晶矽與四層金屬。

本晶片對於數位類比轉換器的電容陣列使用新的切換方式，藉由將最大位元電容切割為其餘電容陣列的排列，且不必額外增加電容。經過推導這樣的方式可以使得在最大位元不論0或1時，消耗能量皆為相同。並且每次位元循環也只需要一個時脈。因應切換方式的改變，新型的控制邏輯也在本論文呈現，包含全客戶式的判定暫存器。

本晶片的操作電壓為1.8V。輸入全刻度訊號0.75V時，類比數位轉換器的消耗為350μW。在取樣頻率為1.1 MS/s、輸入訊號頻率為500 kHz， SNDR約為48db以及有效位元為7.7位元。積分非線性度為0.6 LSB以及差分非線性度0.5 LSB。全晶片的面積為0.8mm×1.3mm，包含墊腳為1.25mm×1.8mm。

Low-power analog-to-digital converter (ADC) is a key element to many applications, especially in portable equipment. A successive approximation register (SAR) ADC used for active pixel sensors is presented. The experimental chip which targets the specification of 320×240 pixel array (QVGA) and 12 frames per second was fabricated using 0.35-μm CMOS mix-signal two-poly and four-metal process.

A noval method for switching the capacitors is utilized for energy-efficiency in the digital-to-analog converter. By splitting the MSB capacitor into the binary scaled sub-capacitors, the approach achieved the same energy whether the MSB is 0 or 1. This requires the same size capacitor array as conventional method and only one clock phase per bit. A new control network is presented for meeting the new switching method. The core of control network is a full-custom decision register.

The chip operates at a supply voltage 1.8V. The ADC consumes 350μW for a full-scale input 0.75V. The SNDR is approximately 48dB and the ENOB is 7.7bit at 1.1 MSamples/s with a 500kHz full-scale sinusoidal input. The static non-linearity is 0.6 INL and 0.5 DNL. The die size is 0.8mm×1.3mm and 1.25mm×1.8mm with pads.

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