本論文可分為三大主要部份：第一部份我們設計一個常見的鎖相迴路，其中包含相位檢測器、電流幫浦、二階低通濾波器、可切換式共振器的壓控振盪器與整數型N除頻器。第二部份中，我們設計一個自我頻率校正電路來校正因振盪器的製程變異而造成的頻率偏移，當鎖相迴路第一次啟動時，此校正迴路進行一次校正，此校正迴路利用偵測頻率偏移的變異，然後相對應地設定共振器的開關來補償此頻率偏移。在第三部份中，我們使用Simulink軟體來預測鎖相迴路中振盪器的頻率跳躍、除頻器的除數值、迴路頻寬與鎖定時間之間的關係，從觀察彼此之間的關係，我們可以找到一個新的方式來應用在超寬頻系統的射頻頻率合成器中。
我們試著整合第一部份與第二部份來建構一個符合GSM/WLAN共存系統的射頻頻率合成器，此頻率合成器不僅提供在GSM與ISM的頻帶中可鎖定所要的頻率，更擁有校正功能來補償因製程變異而造成的頻率偏移；另一方面，也將鎖相迴路的鎖定行為做為一個主題做來研究，藉著將切換式電感整合到壓控振盪器中，利用切換開關來使振盪器的輸出頻率快速跳頻，穩定的迴路由於跳頻的影響而需要一段額外的時間來鎖定振盪頻率，在理想的狀況下，我們發現當迴路頻寬夠大並且除頻器的除數值可同時作調整下，則當頻率跳躍時將不需要額外的時間來鎖定，因此鎖定時間將可小於9.5 ns，使新式的超寬頻射頻頻率合成器將可能被實現。
而此論文的創意貢獻在於：第一，提出並驗證了一個符合GSM/WLAN共存系統的射頻頻率合成器；第二，提出一個新的訊號產生方案來設計超寬頻射頻頻率合成器。

This thesis can be divided into three major parts: In the first part we concern about the design of a general phase lock loop (PLL) including a phase-frequency detector (PFD), a charge pump (CP), a second-order low pass filter (LPF), a voltage controlled oscillator (VCO) with switched resonator, and an integer-N type of frequency divider. In the second part, we design a self-frequency-calibration circuit to correct the frequency shift caused by the process variation in a VCO circuit. The calibration loop would function once when the PLL circuit starts at the first time. The calibration loop detects the variation of frequency shift and correspondingly sets on the switches of the resonator to compensate such frequency shift. In the third part, we use the Simulink software to predict the relation among the frequency jump of VCO, the division number of the frequency divider, the loop bandwidth, and the settling time in a locked PLL. From the observation of such relation, we find a new way of application in an ultra-wide-band (UWB) RF synthesizer.
We try to integrate the results of the first and the second parts to construct an RF synthesizer for the GSM/WLAN co-existence system. Such synthesizer can provide not only the locked local signals for the GSM and the ISM bands as desired but also the calibration function to compensate the frequency shift due to the process variation. On the other hand, a special topic on the locking behavior of a PLL circuit is studied. By integrating a switched inductor into a VCO circuit, the output oscillation frequency can jump quickly by turning the switch on and off. The locked loop is disturbed by this frequency jump and need an extra time to settle on a final oscillation frequency. In an ideal case, we find that there does not need an extra settling time after frequency jumping if the loop bandwidth is wide enough and the division number of the frequency divider can be adjustable simultaneously. This observation make a new design methodology of an UWB RF synthesizer possible because that the switching time can be less than 9.5 ns.
The innovatory contributions of this thesis are: The first, an RF synthesizer is proposed and demonstrated for the GSM/WLAN co-existence system use. The second, a new scheme of signal generation is proposed for the design of an UWB RF synthesizer.

[1] Adil Koukab, Yu Lei and Michel Declercq, “Multi-Standard Carrier Generation System for Quad-band GSM / WCDMA (FDD-TDD) / WLAN(802.11 a-b-g) Radio,” Proceedings of ESSCIRC, Grenoble, France, 2005.
[2] Evangelos S. Angelopoulos, Yorgos E. Stratakos, Antonis I. Kostaridis, Dimitra I. Kaklamani and Nikolaos K. Uzunoglu, “Multiband Miniature Coplanar Waveguide Slot Antennas for GSM-802.11b and 802.11b-802.11a Wireless Applications,” 2003 IEEE, vol.1, Page(s):103 – 108, 16-20 March 2003.
[3] Sotiris Bantas, Yorgos Stratakos*, Nick Kanakaris, Yorgos Katsoulis, Pandelis Papadopoulos, Michael Margaras, Vicky Korou, Hamed Peyravi and Yorgos Koutsoyannopoulos, “Architecture Considerations and Integrated-Passives-Based Design for a Dual-Mode GPRS-WLAN SiGe RF Transceiver,” 2003 IEEE, vol. 4, Page(s):2237 – 2241, 6-9 Oct. 2003.
[4] Mou Shouxian, Ma Jianguo, Yeo Gat Seng, and Do Manh Anh, “An Integrated Dual-band Low Noise Amplifier for GSM and Wireless LAN Applications,” 2003 IEEE, Page(s):67 – 70, 17-20 Sept. 2003.
[5] Ming-Ching Kuo, Chun-Ming Hsu, Chun-Lin KO, Tsung-Hsien Lin, Yi-Bin Lee, “A CMOS WLAN/GPRS Dual-mode RF Front-end Receiver,” 2004 IEEE, Page(s):153 – 156, 6-8 June 2004.
[6] Jan Steinkamp, Frank Henkel and Peter Waldow, “A Multi-Mode Wide-Band 130 nm CMOS VCO for WLAN and GSM/UMTS,” RFIT2005 - IEEE Internatfonal Workshop on Radio-Frequency Integration Technology, Nov 30-Dec 02, 2005.
[7] O. Charlon1, M. Locher, H. Visser, D. Duperray, J. Chen, M. Judson, A. Landesman, C. Hritz, U. Kohlschuetter, . Zhang, C. Ramesh, A. Daanen, M. Gao, S. Haas, V. Maheshwari, A. Bury, G. Nitsche, A. Wrzyszcz, W. Redman-White, H. Bonakdar, R. El Waffaoui, M. Bracey, “A Low-Power High-Performance SiGe BiCMOS 802.11a/b/g Transceiver IC for Cellular and Bluetooth Co-Existence Applications,” Proceedings of ESSCIRC, Grenoble, France, 2005.
[8] 袁帝文等編著, “高頻通訊電路設計,”高立圖書有限公司, 民國93年.
[9] http://cd.tcpd.gov.tw/cgi-bin/SM_theme?page=43a909c9
[10] http://www.cqinc.com.tw/grandsoft/cm/002/002-6.htm
[11] 唐正編著,“802.11無線區域網路通訊協定及應用,”文魁資訊股份有限公司, 民國92年.
[12] http://taiwan.cnet.com/computer/network/features/0,2000068598,20095702,00.htm
[13] A. Batra et al., ”Multi-band OFDM physical layer proposal for IEEE 802.15 Task Group 3a,” IEEE, Piscataway, NJ, IEEE P802.15-03/268r3-TG3a, Mar. 2004.
[14] HOWARD CAM LUONG AND GERRY CHI TAK LEUNG, “LOW-VOLTAGE CMOS RF FREQUENCY SYNTHESIZERS,” Cambridge UK, Cambridge University Press, 2004. New York, NY.
[15] 高曜煌 著, “射頻鎖相迴路IC設計,” 滄海書局, 民國94年.
[16] Behzad Razavi, RF Microelectronics, Prentice-Hall, Inc., 1998.
[17] Adem Aktas Mohammed Ismail, “COMS PLLs and VCOs for 4G Wireless,” Boston, Kluwer Academic, c2004.
[18] Keliu Shu Edgar Sanchez-Sinencio, “CMOS PLL Synthesizers: Analysis and Design,” New York, N.Y., Springer, c2005.
[19] Chia-Jen Wang , “Research on CMOS Frequency Synthesizers for DTV Broadband RF Tuner and DAB Receiver Applications,” Thesis in EE ,NCKU, June 2004.
[20] G. B. Lee, P. K. Chan and L. Siek, “A CMOS Phase Frequency Detector for Charge Pump Phase-Locked Loop,” Circuits and Systems, 1999. 42nd Midwest Symposium on, vol. 2, pp. 601 – 604, Aug. 1999.
[21] Won-Hyo Lee, Jun-Dong Cho and Sung-Dae Lee, “A high speed and low power phase-frequency detector and charge-pump,” Design Automation Conference, 1999. Proceedings of the ASP-DAC '99. Asia and South Pacific, vol.1, pp. 269 – 272, Jan. 1999.
[22] Henrik O. Johansson, “A simple precharged CMOS phase frequency detector,” Solid-State Circuits, IEEE Journal of, pp. 295 – 299, Feb. 1998.
[23] Won-Hyo Lee, Jun-Dong Cho and Sung-Dae Lee, “A high speed and low power phase-frequency detector and charge-pump,” Design Automation Conference, 1999. Proceedings of the ASP-DAC '99. Asia and South Pacific, vol.1, pp. 269 – 272, Jan. 1999.
[24] C. Lam and B. Razavi, “A 2.6/5.2GHz Frequency Synthesizer in 0.4um CMOS Technology,” IEEE J. Solid-State Circuits, vol.35, no.5, pp.788-794, May 2000.
[25] Jia-Lun Wang," Switchable Differential Inductors and Their Application to the Quadrature Oscillator Design for Ultra-Wideband(UWB) RF Synthesizers,” Thesis in EE, NCKU, July 2006.
[26] Byungsoo Chang, Joonbae Park, and Wonchan Kim, “A 1.2 GHz CMOS Dual-Modulus Prescaler Using New Dynamic D-Type Flip-Flops,” IEEE J. of Solid-State Circuits, vol. 31, NO. 5, May 1996.
[27] J. Navarro Soares, Jr., and W. A. M. Van Noije, “A 1.6-GHz Dual Modulus Prescaler Using the Extended True-Single-Phase-Clock CMOS Circuit Technique (E-TSPC),” IEEE J. of Solid-State Circuits, vol. 34, NO. 1, January 1999.
[28] T.-H. Lin and W. J. Kaiser, “A 900-MHz 2.5-mA CMOS Frequency Synthesizer with an Automatic SC Tuning Loop,” IEEE J. of Solid-State Circuits, vol. 36, pp. 424-431, Mar. 2001.
[29] W. B. Wilson, U.-K. Moon, K. R. Lakshmikumar, and L. Dai, “A CMOS Self-Calibrating Frequency Synthesizer,” IEEE J. of Solid-State Circuits, vol. 35, pp. 1437-1444, Oct. 2000.
[30] Yu-Jen Lai and Tsung-Hsien Lin, “A 10-GHz CMOS PLL with an Agile VCO Calibration,” IEEE International Sloid-State Circuits Conference, 8-6, February 2005.
[31] C. Mishra, et. al., “Frequency Planning and Synthesizer Architectures for Multiband OFDM UWB Radios,” IEEE Trans. on Microwave Theory and Techniques, vol.53, issue 12, pp.3744-3756, Dec. 2005.
[32] Tzuen-His Huang, Jia-Lun Wang and Jun-Yuan Wang, “An RF Synthesizer for MB-OFDM UWB Mode-1/Mode-2 Applications,” on filing.
[33] Hsin-Hung Kuo, “Research on 2GHz and 5GHz CMOS Frequency Synthesizer RFICs For 802.11 WLAN,” Thesis in EE, NCKU, June 2004.
[34] Chung When Lo, Palo Alto, CA (US); Keng Leung Fung, Sunnyvale, CA (US), “FREQUENCY SYNTHESIZER WITH AUTOMATIC TUNING CONTROL TO INCREASE TUNING RANGE,” Ralink Technology, Inc., Cupertino, CA (US), US 7,019,595 B1, Mar. 28, 2006.
[35] David R. Welland, Austin, TX (US); Caiyi Wang, Austin, TX (US), “METHOD AND APPARATUS FOR ADJUSTING A DIGITAL CONTROL WORD TO TUNE SYNTHESIZER HIGH-FREQUENCY SIGNALS FOR WIRELESS COMMUNICATIONS,” Silicon Laboratories Inc., Austin, TX (US), US 6,574,288 B1, Jun. 3, 2003.
[36] Christopher Lam, Rowland Heights, CA (US); Thai Nguyen, San Jose, CA (US); Chet Sooraparth, Mountain View, CA (US), “PHASE-LOCKED LOOP WITH SELF-SELECTING MULTI-BAND VCO,” RF Micro Devices, Inc., Greensboro, NC (US), US 6,806,786 B1, Oct. 19, 2004.
[37] Tzuen-His Hiang, Tou-Liu (TW), “QUADRATURE OSCILLATOR,” Industrial Technology Research Institute, Hsinchu (TW), US 6,456,167 B1, Sep. 24, 2002.
[38] Andreani, P.; Bonfanti, A.; Romano, L.; Samori, C.; “Analysis and design of a 1.8-GHz CMOS LC quadrature VCO,” Solid-State Circuits, IEEE Journal of, vol. 37, pp. 1737-1747, Dec. 2002.
[39] Hyoung Chul Choi, So Bong Shin, and Sang-Gug Lee, “A Low-Phase Noise LC-QVCO in CMOS Technology,” IEEE microwave and wireless components letters, vol. 14, no.11, pp. 540-542, November 2004.
[40] Takeshi Yasunaga, Shunsuke Hirano, Masakatsu Maeda*, Yukio Hiraoka*, Toshiakira Andou**, and Yasunori Miyahara, “A Fully Integrated PLL Frequency Synthesizer LSI for Mobile Communication System,” Radio Frequency Integrated Circuits (RFIC) Symposium, 2001. Digest of Papers. 2001 IEEE, pp. 65-68, May 2001.
[41] Chun-Yi Kuo, Che-Fu Liang, and Shen-Iuan Liu, “A 5.8-/5.2-/2.4-GHz SiGe LC VCO with Wide Tuning Range,” IEEE 2004 VLSI/CAD, Taiwan, 5.2, 2004.
[42] Zhenbiao Li and Kenneth K.O., “A 1-V Low Ohase Noise Multi-band CMOS Voltage Control Oscillator with Switched Inductors and Capacitors,” 2004 IEEE Radio Frequency Integrated Circuit Symposium, pp. 467-470, 2004