本論文為使用注入鎖定技術之24-GHz CMOS鎖相迴路式雷達感測器積體電路設計，利用此晶片並採用都卜勒雷達之概念將來可實現一非接觸式感測週期性移動物體設計，可應用於偵測人體呼吸與心跳之生理訊號或是相關的感測器;本架構設計在K頻段，優勢在於有短波長之特性，對於感測生理訊號可更加準確，其應用天線也可微小化。利用自我注入鎖定振盪器並結合鎖相迴路的技術可有效降低相位雜訊並提高訊號雜訊比，此外不需任何解調電路即可於鎖相迴路中的自我注入鎖定振盪器控制電壓端獲得生理訊號資訊。感測機制主要是以鎖相迴路穩定輸出一振盪訊號去偵測生理訊號，而經由人體反射的訊號上載有生理訊號會使自我注入振盪器輸出相位受到擾動，而鎖相迴路機制，本身會轉換出一控制電壓欲使振盪器回復本身之振盪頻率，於是控制電壓上將會有因注入訊號與迴路機制拉扯所造成的微小變動，此控制電壓便為本論文架構所要提取的解調訊號。
本論文所使用之鎖相迴路整合自我注入振盪器與在交互耦合對注入技巧除三除頻器。在自我注入振盪器的設計中，使用N-MOS only的LC-tank架構加上一組注入電晶體，並用MIM電容與可變電容串聯，改善可變電容操作於高頻品質因子較差之問題，也可降低振盪器的增益(Kvco)隨控制電壓的變動量，有益於整體迴路濾波器之設計;而除頻器第一級使用交互耦合對注入技巧除三除頻器，可有效減少直流功率消耗，且透過交互耦合對注入技巧可增強共振腔諧波項之特性，達到較大的除頻範圍，利於整體電路之整合。
本論文之晶片皆採用TSMC 0.18-μm CMOS製程設計實現，電路設計使用Agilent ADS進行模擬，並採用On Wafer Measurement with PCB Bias Network的方式進行量測，整體電路當參考訊號為243 MHz且無注入訊號時，可鎖定在23.328 GHz，其所量測到的相位雜訊在頻率位移1 MHz時約為-87.47 dBc/Hz，輸出功率為-6.2 dBm;而當有注入訊號22.8 GHz且功率為0 dBm時，本電路之輸出頻率可成功鎖定在22.8 GHz，此時所量測到的相位雜訊為-129.81 dBc/Hz，輸出功率為-4.86 dBm;在電路鎖定範圍量測方面，當注入功率為0 dBm時，電路整體鎖定範圍為1.5 GHz。本論文所設計之電路可提供足夠的鎖定範圍，並具有低功耗以及低複雜度之特點，整體晶片面積為4.55 mm2，總功率消耗不含緩衝放大器為36.01 mW。

This thesis presents a 24-GHz CMOS PLL-based radar sensor integrated circuit design with injection-locked technique. This design is based on the Doppler effect that can be used to achieve a non-contact detection technique for measuring a periodic movement, such as vital signs like respiration and heartbeat. The K-band sensors have advantages over lower frequency systems. First, the shorter wavelength is, the more accuracy of detect the vital sign can be. Second, due to the short wavelength at K-band, the antenna size can be reduced properly. The proposed system takes advantages of phase-locked loops and self-injection-locked oscillators with low phase noise and high power spectral SNR gain. The vital-sign signal can be obtained by directly extracting the tuning voltage of the injection-locked voltage-controlled oscillator(ILO) which is controlled by the phase-locked loop without using any demodulation circuits. At the initial stage, the cardiopulmonary motion is detected once the output frequency of the phase-locked loop is stabilized, then the phase variation of the reflected signal is injected into the injector of the ILO. The mechanism of the loop transform the control voltage for tuning the intrinsic oscillation frequency of the VCO. As the result, the ILO fine tuning voltage controlled by the PLL is the vital sign output voltage that reflect the phase variation of the Doppler signal.
The proposed phase-locked loop adopts ILO and a divide-by-three injection-locked frequency divider with injection-switched cross-coupled pair technique. In this ILO circuit, which consists a pair of injectors, a LC-tank oscillator with a varactor tuning series the MIM capacitors which can not only redefine the bias voltage of the varactor and decrease the variation of the VCO gain (KVCO) in circuit design, but also increase the quality factor of the oscillator. The divide-by-three injection-locked frequency divider with injection-switched cross-coupled pair technique is used as the first stage of the divider chain with the advantage of low power consumption and wide locking range by enhancing the harmonic signal in the LC-tank.
In this thesis, the chips are implemented in a TSMC 0.18-μm CMOS process. The Agilent ADS are used for circuit simulation. The chip measurements were done on chip-on-board which with the input and output RF pads probed by the RF wafer probes and all dc voltage supply pads are wire bonded on the PCB board. The system using a 243 MHz reference clock without an injection signal is stabilized at 23.328 GHz. The measured output phase noise at 1-MHz offset from the center frequency of system without injection is -87.47 dBc/Hz and the output power is -6.2 dBm. In the locking situation, the phase noise measurement results with injection signal of 22.8 GHz at the input power of 0 dBm is -129.81 dBc/Hz at 1-MHz offset and the output power is -4.85 dBm. The measured locking range of the proposed circuit at the injection power of 0 dBm, which is approximately 1.5 GHz. The advantages of this design are low circuit complexity, low power consumption and a reasonable locking range. The total chip area is 4.55 mm2 and the power consumption without the output buffer is 36.01 mW.

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