本論文提出一個八位元每秒取樣一百億次的雙通道類比至數位轉換器，其子通道採用由電壓至時間轉換器與時間至數位轉換器構成的時域類比至數位轉換器。為了達到較高能源效率與降低延遲電路帶來的時間不匹配和抖動，本設計針對時間至數位轉換器進行架構的分析與優化，採用可達到次皮秒時間解析度的逐漸趨近式時間至數位轉換器。得利於時域操作的特性，其逐漸逼近式操作可管線化，較高的子通道速度降低所需的通道數量，有效減少時序偏移與通道不匹配對轉換器的影響。
本設計以台積電28奈米CMOS製程進行晶片下線驗證，核心電路面積為0.0216 mm^2。當晶片操作在每秒取樣一百億次與電源電壓0.9伏特時消耗功率為39.78毫瓦並得到奈奎斯特頻率的訊號雜訊失真比/有效位元40.08-dB/6.37位元。換算得到的轉換效率為47.8fJ/conversion-step。

This thesis presents an 8-bit 10-GS/s 2-channel Time-Interleaved ADC (TI-ADC) whose sub-channel is a Time-Domain ADC composed of a voltage-to-time converter (VTC) and a time-to-digital converter (TDC). To achieve energy efficient and also reduce the time mismatch and jitter introduced by delay cells, an analysis and optimization is applied to develop the architecture of the TDC. Based on the analysis results, a successive approximation TDC with sub-picosecond time resolution is implemented. Benefiting from the characteristics of time-domain operations, its successive approximation operation can be pipelined, resulting in higher sub-channel conversion speeds, which reduce the required number of channels and effectively mitigate the impact of timing skew and channel mismatch on the converter.
The proof-of-concept prototype was designed and fabricated in a TSMC 28-nm CMOS technology. The core area occupies 0.0216 mm^2. Operating at 10-GS/s, the power consumption of the ADC is 39.78mW from 0.9-V supply with an ENOB/SNDR of 6.37 bits/40.08dB at Nyquist frequency, leading to a 47.8-fJ/conversion-step Walden figure of merit.

[1] B. Murmann, “ADC Performance Survey 1997-2023,” [Online]. Available: https://web.stanford.edu/~murmann/adcsurvey.html
[2] E. Swindlehurst et al., “An 8-bit 10-GHz 21-mW Time-Interleaved SAR ADC With Grouped DAC Capacitors and Dual-Path Bootstrapped Switch,” in IEEE Solid-State Circuits Letters, vol. 2, no. 9, pp. 83-86, Sept. 2019.
[3] E. Martens, D. Dermit, M. Shrivas, S. Nagata and J. Craninckx, “A Compact 8-bit, 8 GS/s 8×TI SAR ADC in 16nm with 45dB SNDR and 5 GHz ERBW,” 2021 Symposium on VLSI Circuits - Digest of Technical Papers, Kyoto, Japan, 2021.
[4] M. Chu, P. Jacob, J. -W. Kim, M. R. LeRoy, R. P. Kraft and J. F. McDonald, “A 40 Gs/s Time Interleaved ADC Using SiGe BiCMOS Technology,” in IEEE Journal of Solid-State Circuits, vol. 45, no. 2, pp. 380-390, Feb. 2010.
[5] I. -M. Yi, N. Miura, H. Fukuyama and H. Nosaka, “A 15.1-mW 6-GS/s 6-bit Single-Channel Flash ADC With Selectively Activated 8× Time-Domain Latch Interpolation,” in IEEE Journal of Solid-State Circuits, vol. 56, no. 2, pp. 455-464, Feb. 2021.
[6] J. Liu, M. Hassanpourghadi and M. S. -W. Chen, “A 10-GS/s 8-bit 2850-μm2 Two-Step Time-Domain ADC With Speed and Efficiency Enhanced by the Delay-Tracking Pipelined-SAR TDC,” in IEEE Journal of Solid-State Circuits, vol. 57, no. 12, pp. 3757-3767, Dec. 2022.
[7] M. Zhang, Y. Zhu, C. -H. Chan and R. P. Martins, “An 8-Bit 10-GS/s 16× Interpolation-Based Time-Domain ADC With <1.5-ps Uncalibrated Quantization Steps,” in IEEE Journal of Solid-State Circuits, vol. 55, no. 12, pp. 3225-3235, Dec. 2020.
[8] Q. Chen, Y. Liang, C. C. Boon and Q. Liu, “17.8 A Single-Channel 10GS/s 8b>36.4d8 SNDR Time-Domain ADC Featuring Loop-Unrolled Asynchronous Successive Approximation in 28nm CMOS,” 2023 IEEE International Solid-State Circuits Conference (ISSCC) Digest of Technical Papers, San Francisco, CA, USA, 2023, pp. 278-280.
[9] B. Razavi, “The Bootstrapped Switch [A Circuit for All Seasons],” in IEEE Solid-State Circuits Magazine, vol. 7, no. 3, pp. 12-15, Summer 2015.
[10] S. Le Tual, P. N. Singh, C. Curis and P. Dautriche, “22.3 A 20GHz-BW 6b 10GS/s 32mW time-interleaved SAR ADC with Master T&H in 28nm UTBB FDSOI technology,” 2014 IEEE International Solid-State Circuits Conference (ISSCC) Digest of Technical Papers, San Francisco, CA, USA, 2014.
[11] Y. Duan and E. Alon, “A 12.8 GS/s Time-Interleaved ADC With 25 GHz Effective Resolution Bandwidth and 4.6 ENOB,” in IEEE Journal of Solid-State Circuits, vol. 49, no. 8, pp. 1725-1738, Aug. 2014.
[12] M. Wagih Ismail and H. Mostafa, “A new design methodology for Voltage-to-Time Converters (VTCs) circuits suitable for Time-based Analog-to-Digital Converters (T-ADC),” 2014 27th IEEE International System-on-Chip Conference (SOCC), Las Vegas, NV, USA, 2014.
[13] Y. -J. Chen, K. -H. Chang and C. -C. Hsieh, “A 2.02–5.16 fJ/Conversion Step 10 Bit Hybrid Coarse-Fine SAR ADC With Time-Domain Quantizer in 90 nm CMOS,” in IEEE Journal of Solid-State Circuits, vol. 51, no. 2, pp. 357-364, Feb. 2016.
[14] M. Zhang, K. Noh, X. Fan and E. Sánchez-Sinencio, “A 0.8–1.2 V 10–50 MS/s 13-bit Subranging Pipelined-SAR ADC Using a Temperature-Insensitive Time-Based Amplifier,” in IEEE Journal of Solid-State Circuits, vol. 52, no. 11, pp. 2991-3005, Nov. 2017.
[15] D. -R. Oh, J. -I. Kim, D. -S. Jo, W. -C. Kim, D. -J. Chang and S. -T. Ryu, “A 65-nm CMOS 6-bit 2.5-GS/s 7.5-mW 8x Time-Domain Interpolating Flash ADC With Sequential Slope-Matching Offset Calibration,” in IEEE Journal of Solid-State Circuits, vol. 54, no. 1, pp. 288-297, Jan. 2019.
[16] Y. Xu, G. Wu, L. Belostotski and J. W. Haslett, “5-bit 5-GS/s Noninterleaved Time-Based ADC in 65-nm CMOS for Radio-Astronomy Applications,” in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 12, pp. 3513-3525, Dec. 2016.
[17] M. Zhang, C. -H. Chan, Y. Zhu and R. P. Martins, “A 0.6-V 13-bit 20-MS/s Two-Step TDC-Assisted SAR ADC With PVT Tracking and Speed-Enhanced Techniques,” in IEEE Journal of Solid-State Circuits, vol. 54, no. 12, pp. 3396-3409, Dec. 2019.
[18] D. Miyashita, H. Kobayashi, J. Deguchi, S. Kousai and M. Hamada, “A −104dBc/Hz in-band phase noise 3GHz all digital PLL with phase interpolation based hierarchical time to digital convertor,” 2011 Symposium on VLSI Circuits - Digest of Technical Papers, Kyoto, Japan, 2011, pp. 112-113.
[19] H. Chung, H. Ishikuro and T. Kuroda, “A 10-Bit 80-MS/s Decision-Select Successive Approximation TDC in 65-nm CMOS,” in IEEE Journal of Solid-State Circuits, vol. 47, no. 5, pp. 1232-1241, May 2012.
[20] H. Wang and J. Lee, “A 21-Gb/s 87-mW Transceiver With FFE/DFE/Analog Equalizer in 65-nm CMOS Technology,” in IEEE Journal of Solid-State Circuits, vol. 45, no. 4, pp. 909-920, April 2010.
[21] J. Hao et al., “10.2 A Single-Channel 2.6GS/s 10b Dynamic Pipelined ADC with Time-Assisted Residue Generation Scheme Achieving Intrinsic PVT Robustness,” 2023 IEEE International Solid-State Circuits Conference (ISSCC) Digest of Technical Papers, San Francisco, CA, USA, 2023.
[22] Zhu. Shuang., “Time-Domain Analog-to-Digital Conversion and Gigahertz Time-Domain Folding/Flash ADC,” Ph.D. thesis, The University of Texas at Dallas, TX, USA, 2017.