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| 研究生： |
陳建宏 Chen, Chien-Hung |
|---|---|
| 論文名稱： |
高介電常數金屬閘極鰭式場效應電晶體特性三維電性模擬及高遷移率矽鍺通道之研究 The Investigations and 3D Simulations of the Characteristics of Advanced HKMG Bulk FinFETs and SiGe Channels with High Mobility |
| 指導教授： |
朱聖緣
Chu, Sheng-Yuan |
| 學位類別： |
博士 Doctor |
| 系所名稱： |
電機資訊學院 - 電機工程學系 Department of Electrical Engineering |
| 論文出版年： | 2014 |
| 畢業學年度： | 103 |
| 語文別： | 英文 |
| 論文頁數： | 76 |
| 中文關鍵詞： | 鰭型場效電晶體 、可變電容 、元件模擬 、光學臨界尺度模型 、矽鍺通道鰭式場效電晶體 、鍺載子遷移率 、介面粗糙度 、矽鍺 |
| 外文關鍵詞： | FinFET, varactor, Device Simulation, optical critical dimension model, SiGe channel FinFETs, Ge concentration Mobility, Interface Roughness, Silicon Germaniums |
| 相關次數： | 點閱：131 下載：8 |
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近年來，根據國際半導體技術藍圖(ITRS romap)，電晶體尺寸不斷的微縮，已經來到次奈米級世代，各種製程步驟皆更加的繁雜，每個步驟背後需要仰賴更多技術的克服，因此若想要電晶體得以維持摩爾定律(Moore's Law)繼續微縮，除了傳統製程技術上的突破創新，電晶體結構上的創新，是次奈米級甚至奈米級電晶體勢必要有的革新 。在次微米的技術節點下，鰭式場效應電晶體是一個十分受關注的研究與發展方向，因為其具有更好的截止頻率、短通道效應的控制能力、和優異的微縮能力；最近雖然有許多鰭式場效應電晶體相關的實驗與理論的研究被提出，但只有少許的研究有討論到有關這種三維度電晶體佈局參數，例如：鰭通道寬度對於鰭式場效應電晶體的電特性影響。
在此篇文章中，我們實際做出及量測高介電常數金屬閘極塊狀鰭式場效電晶體的特性，並模擬在不同錐狀與彎角下鰭狀通道的外型。在此，將估計不同錐狀與彎角下對C-V曲線的影響，並簡單敘述製成參數。鰭式場效電晶體變容器的鰭狀通道在不同錐狀角度與彎角半徑下，變容器的CV曲線變化。我們可發現當鰭狀通道的錐狀角度越陡峭，元件的電容值就越小。以及當鰭狀通道的彎角半徑越大，工作在累積區的元件的最小電容值就越小。最後，我們比較模擬結果和製程實驗的資料數據，發現其結論相符。並且研究空乏區電容效應在傳統平面元件與鰭式場效電晶體變容器的不同， N-型鰭式場效電晶體變容器的空乏區電容相較於傳統的體平面場效電晶體變容器還要低因此N-型鰭式場效電晶體變容器提供了較大的可調變電容區。鰭式與傳統的體平面場效電晶體變容器的三維模擬證明了鰭式場效電晶體變容器對於施加於閘極的電壓更為靈敏。首度探討在高介電常數金屬閘極鰭式場效應電晶體中，以矽為材料的鰭狀通道其寬度與電特性的相關性。在同樣的佈局區域中，我們的實驗與模擬研究指出寬度窄的鰭狀通道擁有較差的平帶電壓位移，且由於基板電阻的增加，閘極電容上有較大的變動。
第二部分研究以矽鍺為材料的鰭狀通道,鍺濃度在鰭式場效電晶體扮演相當重要的角色,因此,快速,非破壞性分析方法,三維度的光譜橢圓偏振光學臨界尺度量測被用來擷取出在矽鍺通道中鍺的濃度。 我們研究在波長370nm與525nm下,不同鍺濃度下的折射係數(n)與消光系數(k).研究結果出在矽鍺通道中鍺的濃度可以精準地三維度的光譜橢圓偏振光學臨界尺度量測法取得. 接著分析高解析度穿透式電子顯微鏡下求得的矽鍺與氧化層介面的表面粗糙度 將載子遷移率相依表面粗糙度模型放入半導體元件模型來研究沿著晶格常數(100) 與(110)的矽鍺載子遷移率,並且進一步分析研究表面粗糙度對矽鍺載子遷移率對於有效載子遷移率的影響。
For these years, according to ITRS roadmap, the size of device keeps scaling. It comes to nanodevice’s generation, each step of process technology has become more complicated, and this is based on more breakthrough of technology. If we want to keep scaling based on Moore’s Law technology, in addition to the breakthroughs and innovations for traditional process technology, the innovation of transistor structure for sub-nano-or even nanoscale transistors is the key-point. Bulk FinFET is one of the candidates for device in sub-22 nm technology node, because of its good cut-off characteristics, short channel effect control and better scalability by double gate mode operation. Recent researches on FinFET devices were reported, but there are few reports discuss the influence of layout parameter, such as fin width, fin height, and the fin numbers, on the electrostatic characteristic of the devices.
In the first part of this thesis, we experimentally fabricate and characterize high-k metal gate (HKMG) bulk FinFET devices, and simulate the fin profile with different tapers and rounding. The effect of the fin taper and rounding profile on the C-V characterization is assessed by extracting the fabrication parameters accordingly. The capacitance-voltage electrical characteristics of fin field-effect transistor (FinFET) varactors which have fins with different taper angles and rounding radiuses are investigated. By fitting the results of the three-dimensional correction simulation with those of an experimentally fabricated FinFET varactor, two key factors of process simulations (taper angles θ and rounding radius r) are extracted. It is found that the the capacitance of the FinFET varactor changes when the fin cross-sectional profile varies. The examination presented here is useful in the fabrication of FinFETs. It clarifies the fin cross-sectional profile effect on the FinFET varactor capacitance. The effects of the depletion capacitance of a varactor between fin field-effect Transistor (FinFET) and bulk planar devices are investigated. The depletion capacitance of an NMOS varactor in FinFETs is lower than that of the conventional bulk planar one. Thus, the NMOS FinFET varactor provides a larger tuning range than the bulk planar one. The simulation results of the proposed 3D devices with FinFET and bulk planar varactors show that the depletion layer width of the NMOS varactors in FinFETs is more sensitive to the applied gate voltage than the bulk planar one. We for the first time explore the dependence of the silicon fin width on the electrostatic characteristic of HKMG bulk FinFET devices. On the same layout area, our study indicates that the narrow fin width possesses worse flat band voltage shift and large variation of gate capacitance owing to increased substrate resistance.
In the second part of this thesis, the interface roughness between the Si(1-x)Gex (x=0.25) and SiO2 is experimentally extracted and calculated as a function of root mean square by analysis of high resolution transmission electron microscopy. The surface-roughness dependent mobility model is then incorporated into device simulation to study the mobility of SiGe along (110) and (100) orientations of the devices. We further analyze four devices with different surface roughness along (100) and (100) orientations to demonstrate the influence of surface roughness on the total effective mobility. The Ge concentration play an important role in SiGe channel Fin-FET device. A fast, more convenient, and nondestructive analysis method, three-dimensional spectroscopic ellipsometry-optical critical dimension metrology (3D SE-OCD), is used to extract Ge concentrations of SiGe channel FinFETs. The refractive index (n) and extinction index (k) of SiGe with different Ge concentrations investigated under wavelengths ln = 370 nm and lk = 525 nm. Results show that the Ge concentration of SiGe channel can be accurately measured using a 3D SE-OCD.
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