在現今的晶片設計中，電源網路規劃(Powerplanning)是一個非常重要的階段。像是在先進製程中，晶片設計可能有更嚴重的電壓下降且隨著設計複雜度急遽上升，造成晶片有更大的功率消耗。傳統的電源網路規劃法通常只考慮靜態的功率消耗而忽略的動態功耗的問題，這樣會導致使用過多的電源網路線，使得其在繞線階段時晶片上產生不可繞的區域。因此在做電源網路規劃時是必須去考慮動態功耗，其中在考慮動態功耗時是更困難的問題，因為晶片的功耗會隨著時間有所變化。更重要的是，必須在滿足動態壓降約束的同時考慮晶片的可繞度。
在本論文中，我們提出一個可靠且有效的電源網路優化法，在考慮動態壓降約束下優化電源網路，同時考慮了最小化繞線面積。我們的方法包含叢集階段和優化階段。在叢集階段，我們提出一個叢集演算法將所有的功率檔案分成幾個群組，而每個群組中的功率檔案有著相似的功率分佈情形。接著我們會從大量的功率檔案中選出代表者，接著為了滿足動態壓降約束，優化階段會藉由選出的代表者建立壓降違規圖，並依據該圖改善壓降違規。根據我們所提出的方法可以有效地解決壓降違規，並且不會使用過多的繞線資源。實驗結果顯示，此方法能在實際工業使用之電路取得了不錯的成果。

Powerplanning is a critical stage in physical design, powerplanning has become a more important stage in a modern VLSI design flow. As design complexity continues increases, a design consumes more an more power. Most of previous works only consider static power consumption without handling dynamic power consumption which may lead to routing congestion in signal net routing. Moreover, it is necessary to consider dynamic power since power consumption of a design changes over time. This problem is much more difficult than that only considers static power because power consumption of a design vary as time. More importantly, it has to consider routability while meeting the dynamic IR-drop constraint.
In this paper, we propose an efficient and effective approach to optimize power network considering dynamic IR-drop. We apply the clustering based algorithm to divide power profiles into several groups such that power profiles in each group have with similar power distribution in a chip. Moreover, we select representative power profiles from a large number of power profiles. Then, the post-optimization stage apply an iterative approach to optimize power network according to critical power profile one by one until all IR-drop violation are fixed. According to the proposed approach, our approach can repair voltage violations efficiently without consuming excessive routing area. The experimental results show the proposed methodology achieves promising results in industry designs.

[1] J.-M. Lin, J.-S. Syu and I.-R. Chen, “Macro-Aware Row-Style Power Delivery Network Design for Better Routability,” in Proc. ICCAD, Nov. 2018.
[2] S.S.-Y. Liu, C.-J. Lee, C.-C. Huang, H.-M. Chen, C.-T. Lin and C.-H. Lee, “Effective power network prototyping via statistical-based clustering and sequential linear programming,” in Proc. DATE, pp. 1701-1706, 2013.
[3] C. Chu and Y.-C. Wong, “FLUTE: Fast Lookup Table Based Rectilinear Steiner Minimal Tree Algorithm for VLSI Design,” IEEE Trans. on CAD, vol. 27(1), pp. 70-83, Jan 2008.
[4] Y. Zhong and M. D. F. Wong, “Fast algorithms for IR drop analysis in large power grid,” in Proc. ICCAD, Nov. 2005.
[5] H. Qian, S. R. Nassif, and S. S. Sapatnekar, “Random walks in a supply network,” in Proc. Design Automation Conf. (DAC), 2003, pp. 93–98
[6] S. Kose and E. G. Friedman, “Fast Algorithms for IR Voltage Drop Analysis Exploiting Locality,” in Proc. Design Automation Conference, pp. 996–1001, June 2011.
[7] T.-Y. Wang and C.-C. Chen, “Optimization of the Power/Ground Network Wire-Sizing and Spacing Based on Sequential Network Simplex Algorithm,” in Proc. ISQED, pp. 157-162, 2002.
[8] L. Singhal and S. Oh and E. Bozorgzadeh, “Statical Power Profile Correlation for Realistic Thermal Estimation,” in IEEE, Mar. 2008.
[9] W.-H. Chang, M.C.-T. Chao and S.-H. Chen, “Practical Routability-Driven Design Flow for Multilayer Power Networks Using Aluminum-Pad Layer,” IEEE Trans. on VLSI Systems, vol. 22(5), pp. 1069-1081, Jun. 2013.
[10] C.-J. Lee, S.S.-Y. Liu, C.-C. Huang, H.-M. Chen C.-T. Lin and C.-H. Lee, “Hierarchical Power Network Synthesis for Multiple Power Domain Designs,” in Proc. ISQED, pp. 477-482, 2012.
[11] Y. Zhong and M.D.-F. Wong, “Fast Placement Optimization of Power Supply Pads,” in Proc. ASP-DAC, May, 2007.
[12] C. Andrew, K. M. Kim, U. Mallappa, S. Sapatnekar, X. Bangqi, “Template-based PDN synthesis in floorplan and placement using classifier and CNN techniques,” in Proc. ASP-DAC, Jan. 2020.
[13] Z. Xie, H. Ren, B. Khailany, Y. Sheng, S. Santosh, J. Hu, Y. Chen“Transferable dynamic IR drop estimation via maximum convolutional Neural Network,” in Proc. ASP-DAC, Jan. 2020.

[14] I.-R. Chen and J.-M. Lin, “Routabkility-driven Powerplanning with Dynamic Voltage Drop Constraint”
[15] https://www.apacheda.com/products/redhawk
[16] https://www.synopsys.com/support/training/signoff/primetimesi-fcd.html