本論文提出一個具有全晶片化背景時序偏移校正的七位元每秒取樣四十五億次的四通道逐漸趨近式類比數位轉換器，其校正機制具有與輸入不相關、快速收斂、低複雜度的特點。為了達到具備高能源效率以及穩健的子通道，本設計採用了部分迴圈展開式的逐漸趨近式類比數位轉換器。藉由在前四個位元採用迴圈展開式的技術以縮短轉換時間，同時降低粗解析的比較器以及數位邏輯的功耗。粗解析以及細解析比較器的補偏不匹配以及粗解析比較器較大的雜訊可由妥善安排的非二進制電容權重所容忍。在每個子通道的細解析比較器都引入了電荷幫浦式的補偏校正來減少通道間的補偏不匹配。所有校正機制皆於晶片上運作並且對功耗以及面積負擔極小。
　　本設計以台積電28奈米CMOS製程進行晶片下線驗證。核心電路面積為0.029 mm2。當晶片操作在每秒取樣四十五億次與輸入電壓1/1.1伏特時消耗功率為6.56 mW並得到奈奎斯特頻率的有效位元6.31位元。其轉換效率為18.5 fJ/conversion-step，為目前所有大於三億次取樣且大於20奈米製程的作品中的最佳。在接近4 GHz的輸入頻率下，所提出的背景時序偏移校正可以在少於12K個取樣點下抑制時序偏移誤差到<-52 dB。

This thesis presents a 7b 4.5GS/s 4× interleaved SAR ADC with the proposed fully on-chip background timing-skew calibration, which features input-independence, fast convergence and low complexity. To achieve energy-efficient and robust sub-channel, a partial loop-unrolled SAR ADC is adopted. The loop-unrolled technique is manipulated in the first 4 MSBs for the purpose of shortening the conversion time and reducing the power consumption of coarse comparators and digital logics. The offset mismatches between coarse and fine comparators as well as the larger noise in coarse comparators can be tolerated by well-arranged non-binary weighting. A charge-pump-based background offset calibration is adopted in fine comparator of each sub-channel to reduce the offset mismatches among channels. The overall calibrations operate fully on-chip and cost a little power and area overhead.
　　The proof-of-concept prototype was designed and fabricated in a TSMC 28-nm CMOS technology. The core area occupies 0.029 mm2. Operating at 4.5 GS/s, the power consumption of the ADC is 6.56 mW from 1.1/1-V supplies with an ENOB of 6.31 bits at Nyquist frequency. The FoM is 18.5 fJ/conversion-step, which is the best result among state-of-the-art ADCs in technology nodes at or above 20 nm and >=3 GS/s. With a near 4 GHz input, the proposed background timing-skew calibration suppresses the timing-skew tones below -52 dB in <12K samples.

[1] B. Murmann, “ADC Performance Survey 1997-2022,” [Online]. Available: http://web.stanford.edu/~murmann/adcsurvey.html.
[2] L. Kull et al., "A 3.1 mW 8b 1.2 GS/s Single-Channel Asynchronous SAR ADC With Alternate Comparators for Enhanced Speed in 32 nm Digital SOI CMOS," in IEEE Journal of Solid-State Circuits, vol. 48, no. 12, pp. 3049-3058, Dec. 2013.
[3] C.-H. Chan et al., “A 6 b 5 GS/s 4 interleaved 3 b/cycle SAR ADC,” IEEE J. Solid-State Circuits, vol. 51, no. 2, pp. 365–377, Feb. 2016
[4] E. Swindlehurst et al., "An 8-bit 10-GHz 21-mW Time-Interleaved SAR ADC With Grouped DAC Capacitors and Dual-Path Bootstrapped Switch," in IEEE Journal of Solid-State Circuits, vol. 56, no. 8, pp. 2347-2359, Aug. 2021.
[5] M. Zhang et al., "An 8-Bit 10-GS/s 16× Interpolation-Based Time-Domain ADC With <1.5-ps Uncalibrated Quantization Steps," in IEEE Journal of Solid-State Circuits, vol. 55, no. 12, pp. 3225-3235, Dec. 2020.
[6] J. Liu et al., "A 10-GS/s 8-bit 2850- μm2 Two-Step Time-Domain ADC with Speed and Efficiency Enhanced by the Delay-Tracking Pipelined-SAR TDC," in IEEE Journal of Solid-State Circuits, 2022.
[7] B. Razavi, "Design Considerations for Interleaved ADCs," in IEEE Journal of Solid-State Circuits, vol. 48, no. 8, pp. 1806-1817, Aug. 2013.
[8] W. C. Black and D. A. Hodges, "Time interleaved converter arrays," in IEEE Journal of Solid-State Circuits, vol. 15, no. 6, pp. 1022-1029, Dec. 1980.
[9] B. Razavi, "The Bootstrapped Switch [A Circuit for All Seasons]," in IEEE Solid-State Circuits Magazine, vol. 7, no. 3, pp. 12-15, Summer 2015.
[10] B. Wicht et al., "Yield and speed optimization of a latch-type voltage sense amplifier," in IEEE Journal of Solid-State Circuits, vol. 39, no. 7, pp. 1148-1158, July 2004.
[11] P. Nuzzo et al., "Noise Analysis of Regenerative Comparators for Reconfigurable ADC Architectures," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 55, no. 6, pp. 1441-1454, July 2008.
[12] T. Sepke et al., "Noise Analysis for Comparator-Based Circuits," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 56, no. 3, pp. 541-553, March 2009.
[13] H. Xu and A. A. Abidi, "Analysis and Design of Regenerative Comparators for Low Offset and Noise," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, no. 8, pp. 2817-2830, Aug. 2019.
[14] B. Razavi, "The StrongARM Latch [A Circuit for All Seasons]," in IEEE Solid-State Circuits Magazine, vol. 7, no. 2, pp. 12-17, Spring 2015.
[15] C. -C. Liu et al., "A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure," in IEEE Journal of Solid-State Circuits, vol. 45, no. 4, pp. 731-740, April 2010.
[16] G. -Y. Huang et al., "10-bit 30-MS/s SAR ADC Using a Switchback Switching Method," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 21, no. 3, pp. 584-588, March 2013.
[17] T. Jiang et al., "A Single-Channel, 1.25-GS/s, 6-bit, 6.08-mW Asynchronous Successive-Approximation ADC With Improved Feedback Delay in 40-nm CMOS," in IEEE Journal of Solid-State Circuits, vol. 47, no. 10, pp. 2444-2453, Oct. 2012.
[18] Y. -Z. Lin et al., "A 9-Bit 150-MS/s Subrange ADC Based on SAR Architecture in 90-nm CMOS," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 60, no. 3, pp. 570-581, March 2013.
[19] H. -Y. Tai et al., "11.2 A 0.85fJ/conversion-step 10b 200kS/s subranging SAR ADC in 40nm CMOS," 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014, pp. 196-197.
[20] Y. Zhu et al., "A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS," in IEEE Journal of Solid-State Circuits, vol. 45, no. 6, pp. 1111-1121, June 2010.
[21] G. -Y. Huang et al., "A 1-µW 10-bit 200-kS/s SAR ADC With a Bypass Window for Biomedical Applications," in IEEE Journal of Solid-State Circuits, vol. 47, no. 11, pp. 2783-2795, Nov. 2012.
[22] P. J. A. Harpe et al., "A 26 μ W 8 bit 10 MS/s Asynchronous SAR ADC for Low Energy Radios," in IEEE Journal of Solid-State Circuits, vol. 46, no. 7, pp. 1585-1595, July 2011.
[23] C. -P. Huang et al., "Analysis of Nonideal Behaviors Based on INL/DNL Plots for SAR ADCs," in IEEE Transactions on Instrumentation and Measurement, vol. 65, no. 8, pp. 1804-1817, Aug. 2016.
[24] D. Schinkel et al., "A Double-Tail Latch-Type Voltage Sense Amplifier with 18ps Setup+Hold Time," 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 2007.
[25] M. van Elzakker et al., "A 1.9μW 4.4fJ/Conversion-step 10b 1MS/s Charge-Redistribution ADC," 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2008.
[26] Masaya Miyahara et al., "A low-noise self-calibrating dynamic comparator for high-speed ADCs," 2008 IEEE Asian Solid-State Circuits Conference, 2008, pp. 269-272.
[27] H. Jeon and Y. -B. Kim, "A CMOS low-power low-offset and high-speed fully dynamic latched comparator," 23rd IEEE International SOC Conference, 2010, pp. 285-288.
[28] J. -H. Tsai et al., "A 0.003 mm2 10 b 240 MS/s 0.7 mW SAR ADC in 28 nm CMOS With Digital Error Correction and Correlated-Reversed Switching," in IEEE Journal of Solid-State Circuits, vol. 50, no. 6, pp. 1382-1398, June 2015.
[29] C. -C. Liu et al., "A 10 bit 320 MS/s Low-Cost SAR ADC for IEEE 802.11ac Applications in 20 nm CMOS," in IEEE Journal of Solid-State Circuits, vol. 50, no. 11, pp. 2645-2654, Nov. 2015.
[30] J. Yang et al., "A 1 GS/s 6 Bit 6.7 mW Successive Approximation ADC Using Asynchronous Processing," in IEEE Journal of Solid-State Circuits, vol. 45, no. 8, pp. 1469-1478, Aug. 2010.
[31] R. Kapusta et al., "A 14b 80 MS/s SAR ADC With 73.6 dB SNDR in 65 nm CMOS," in IEEE Journal of Solid-State Circuits, vol. 48, no. 12, pp. 3059-3066, Dec. 2013.
[32] J. -H. Tsai et al., "A 1-V, 8b, 40MS/s, 113µW charge-recycling SAR ADC with a 14µW asynchronous controller," 2011 Symposium on VLSI Circuits - Digest of Technical Papers, 2011, pp. 264-265.
[33] G. -Y. Huang et al., "A 10b 200MS/s 0.82mW SAR ADC in 40nm CMOS," 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2013, pp. 289-292.
[34] T. Waho, "Non-binary Successive Approximation Analog-to-Digital Converters: A Survey," 2014 IEEE 44th International Symposium on Multiple-Valued Logic, 2014, pp. 73-78.
[35] W. Liu et al., “A 12-bit 50-MS/s 3.3mW SAR ADC with background digital calibration,” in Proc. IEEE Custom Integrated Circuits Conf. (CICC), 2012, pp. 1–4.
[36] F. Kuttner et al., “A 1.2-V 10-b 20-Msample/s nonbinary successive approximation ADC in 0.13-µm CMOS,” in IEEE Intl. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 2002, pp. 176−177.
[37] S.-W. M. Chen et al., “A 6-bit 600-MS/s 5.3mW asynchronous ADC in 0.13 µm CMOS,” IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 26692680, Dec. 2006.
[38] T. Ogawa et al., “SAR ADC algorithm with redundancy,” in Proc. IEEE Asia Pacific Conf. Circuits Syst. (APCCAS), Nov. 2008, pp. 268–271.
[39] T. Ogawa et al., “Non-binary SAR ADC with digital error correction for low power applications,” in Proc. IEEE Asia Pacific Conf. Circuits Syst. (APCCAS), Dec. 2010, pp. 196199.
[40] H.-Y. Tai et al., “A 3.2 fJ/c.-s. 0.35 V 10 b 100 kS/s SAR ADC in 90 nm CMOS,” in IEEE Symp. VLSI Circuits (SOVC) Dig. Tech. Papers, Jun. 2012, pp. 92–93.
[41] Toru Okazaki, et al., “A Design Technique for a High-speed SAR ADC Using Non-binary Search Algorithm and Redundancy,” in Proc. IEEE Asia Pacific Microwave Conf. (APMC), Dec. 2013, pp. 506508.
[42] Hyeok-Ki Hong et al., “A 7b 1GS/s 7.2mW nonbinary 2b/cycle SAR ADC with register-to-DAC direct control,” in Proc. IEEE Custom Integrated Circuits Conf. (CICC), 2012, pp. 1−4.
[43] C.-C. Liu et al., “A 10b 100MS/s 1.13mW SAR ADC with binary scaled error compensation,” in IEEE Intl. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2010, pp. 386–387.
[44] V. Giannini et al., "An 820μW 9b 40MS/s Noise-Tolerant Dynamic-SAR ADC in 90nm Digital CMOS," 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2008, pp. 238-610.
[45] G. Van der Plas et al., ‘‘A 150 MS/s 133 W 7 bit ADC in 90 nm Digital CMOS,’’ IEEE J. Solid-State Circuits, vol. 43, no. 12, pp. 2631–2640, Dec. 2008.
[46] C. C. Lee and M. P. Flynn, "A SAR-Assisted Two-Stage Pipeline ADC," in IEEE Journal of Solid-State Circuits, vol. 46, no. 4, pp. 859-869, April 2011.
[47] J. -C. Wang and T. -H. Kuo, "A 0.82mW 14b 130MS/S Pipelined-SAR ADC With a Distributed Averaging Correlated Level Shifting (DACLS) Ringamp and Bypass-Window Backend," 2022 IEEE International Solid- State Circuits Conference (ISSCC), 2022.
[48] J. A. Fredenburg and M. P. Flynn, "A 90-MS/s 11-MHz-Bandwidth 62-dB SNDR Noise-Shaping SAR ADC," in IEEE Journal of Solid-State Circuits, vol. 47, no. 12, pp. 2898-2904, Dec. 2012.
[49] Y. -Z. Lin et al., "20.2 A 40MHz-BW 320MS/s Passive Noise-Shaping SAR ADC With Passive Signal-Residue Summation in 14nm FinFET," 2019 IEEE International Solid- State Circuits Conference - (ISSCC), 2019, pp. 330-332.
[50] A. AlMarashli et al., "A Nyquist Rate SAR ADC Employing Incremental Sigma Delta DAC Achieving Peak SFDR = 107 dB at 80 kS/s," in IEEE Journal of Solid-State Circuits, vol. 53, no. 5, pp. 1493-1507, May 2018.
[51] P. J. A. Harpe et al., “A 0.47-1.6mW 5-bit 0.5-1 GS/s time-interleaved SAR ADC for low-power UWB radio,” IEEE J. Solid-State Circuits, vol. 47, no. 7, pp. 1594–1602, July 2012.
[52] M. El-Chammas et al., “A 12-GS/s 81-mW 5-bit Time-Interleaved Flash ADC With Background Timing Skew Calibration,” IEEE J. Solid-State Circuits, vol. 46, no. 4, pp. 838-847, Mar. 2011.
[53] A. Nazemi et al., “A 10.3 GS/s 6 bit (5.1 ENOB at Nyquist) time-interleaved pipelined ADC using open-loop amplifiers and digital calibration in 90 nm CMOS,” in IEEE Symp. VLSI Circuits (SOVC) Dig. Tech. Papers, 2008, pp. 18–19.
[54] P. Harpe et al., “Calibration of Ultra Low-Power Time-Interleaved SAR ADCs,” in Proc. IEEE New Circuits and Systems Conf. Dig. Tech. Papers (NEWCAS), 2012, pp. 361364.
[55] K. Poulton et al., “A 20 GS/s 8 b ADC with a 1 MB memory in 0.18 /spl mu/m CMOS,” in Proc. IEEE International Solid-State Circuits Conference Dig. Tech. Papers (ISSCC), Feb. 2003, pp. 318-496
[56] M.-J. E. Lee et al., ‘‘Low-power area-efficient high-speed I/O circuit techniques,’’ IEEE J. Solid-State Circuits, vol. 35, no. 11, pp. 1591–1599, Nov. 2000.
[57] B. Sung et al., “A 6 bit 2 GS/s flash-assisted time-interleaved (FATI) SAR ADC with background offset calibration,” in IEEE Asian Solid-State Circuits Conf. (A-SSCC) Dig. Tech. Papers, Nov. 2013, pp. 281–284.
[58] J. A. McNeill et al., “Split ADC calibration for all-digital correction of time-interleaved ADC errors,” IEEE Trans. Circuits and Systems I: Express Briefs, vol. 56, no. 5, pp. 344–348, May 2009.
[59] C. Hsu et al., “An 11b 800MS/s Time-interleaved ADC with,” in IEEE Intl. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2007, pp. 464-615
[60] W. Liu et al., “A 600MS/s 30mW 0.13μm CMOS ADC Array Achieving Over 60dB SFDR with Adaptive Digital Equalization,” in IEEE Intl. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2009, pp. 82-83.
[61] K. Doris et al., “A 480mW 2.6GS/s 10b 65nm CMOS Time-Interleaved ADC with 48.5db SNDR up to Nyquist,” in IEEE Intl. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2011, pp. 180-182.
[62] A. M. A. Ali et al., "A 12-b 18-GS/s RF Sampling ADC With an Integrated Wideband Track-and-Hold Amplifier and Background Calibration," in IEEE Journal of Solid-State Circuits, vol. 55, no. 12, pp. 3210-3224, Dec. 2020.
[63] L. Kull et al., "A 24-to-72GS/s 8b time-interleaved SAR ADC with 2.0-to-3.3pJ/conversion and >30dB SNDR at nyquist in 14nm CMOS FinFET," 2018 IEEE International Solid - State Circuits Conference - (ISSCC), 2018, pp. 358-360.
[64] M. Guo et al., "Background Timing Mismatch Calibration Techniques in High-Speed Time-Interleaved ADCs: A Tutorial Review," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 69, no. 6, pp. 2564-2569, June 2022.
[65] D. Stepanovic and B. Nikolic, "A 2.8 GS/s 44.6 mW Time-Interleaved ADC Achieving 50.9 dB SNDR and 3 dB Effective Resolution Bandwidth of 1.5 GHz in 65 nm CMOS," in IEEE Journal of Solid-State Circuits, vol. 48, no. 4, pp. 971-982, April 2013.
[66] M. Guo et al., "A 1.6-GS/s 12.2-mW Seven-/Eight-Way Split Time-Interleaved SAR ADC Achieving 54.2-dB SNDR With Digital Background Timing Mismatch Calibration," in IEEE Journal of Solid-State Circuits, vol. 55, no. 3, pp. 693-705, March 2020.
[67] H. -W. Kang et al., "A Time-Interleaved 12-b 270-MS/s SAR ADC With Virtual-Timing-Reference Timing-Skew Calibration Scheme," in IEEE Journal of Solid-State Circuits, vol. 53, no. 9, pp. 2584-2594, Sept. 2018.
[68] T. Oshima et al., “LMS calibration of sampling timing for time-interleaved A/D converters,” Electron. Lett., vol. 45, no. 12, pp. 615–617, Jun. 2009.
[69] N. Le Dortz et al., "22.5 A 1.62GS/s time-interleaved SAR ADC with digital background mismatch calibration achieving interleaving spurs below 70dBFS," 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014
[70] H. Le Duc et al., "Fully Digital Feedforward Background Calibration of Clock Skews for Sub-Sampling TIADCs Using the Polyphase Decomposition," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 64, no. 6, pp. 1515-1528, June 2017.
[71] B. Sung et al., “A 21fJ/conv-step 9 ENOB 1.6GS/s 2× Time-Interleaved FATI SAR ADC with Background Offset and Timing-Skew Calibration in 45nm CMOS,” in Proc. IEEE International Solid-State Circuits Conference Dig. Tech. Papers (ISSCC), Feb. 2015, pp. 1–3.
[72] S. Lee et al., “A 1GS/s 10b 18.9mW Time-Interleaved SAR ADC with Background Timing-Skew Calibration,” in Proc. IEEE International Solid-State Circuits Conference Dig. Tech. Papers (ISSCC), Feb. 2014, pp. 384–385
[73] J. Song et al., "A 10-b 800-MS/s Time-Interleaved SAR ADC With Fast Variance-Based Timing-Skew Calibration," in IEEE Journal of Solid-State Circuits, vol. 52, no. 10, pp. 2563-2575, Oct. 2017
[74] J. Song et al., "A 10-b 600-MS/s 2-Way Time-Interleaved SAR ADC With Mean Absolute Deviation-Based Background Timing-Skew Calibration," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, no. 8, pp. 2876-2887, Aug. 2019.
[75] H. Wei et al., “An 8 bit 4 GS/s 120 mW CMOS ADC,” IEEE J. Solid-State Circuits, vol. 49, no. 8, pp. 1751–1761, Aug. 2014.
[76] V. H-C. Chen et al., “A 69.5mW 20GS/s 6b time-interleaved ADC with embedded time-to-digital calibration in 32nm CMOS SOI,” in Proc. IEEE International Solid-State Circuits Conference Dig. Tech. Papers (ISSCC), pp. 380–381, Feb. 2014.
[77] S. M. Jamal et al., "A 10-b 120-Msample/s time-interleaved analog-to-digital converter with digital background calibration," IEEE J. Solid-State Circuit, vol. 37, no. 12, pp. 1618-1627, 2002.
[78] C. Chen et al., "A 10-b 500MS/s Partially Loop-Unrolled SAR ADC with a Comparator Offset Calibration Technique," 2021 IEEE International Symposium on Circuits and Systems (ISCAS), 2021
[79] H. Wang and J. Lee, "A 21-Gb/s 87-mW Transceiver With FFE/DFE/Analog Equalizer in 65-nm CMOS Technology," in IEEE Journal of Solid-State Circuits, vol. 45, no. 4, pp. 909-920, April 2010
[80] El-Chammas, Manar, and Boris Murmann. Background calibration of time-interleaved data converters. Springer Science & Business Media, 2011.
[81] B. Razavi, "The Flash ADC [A Circuit for All Seasons]," in IEEE Solid-State Circuits Magazine, vol. 9, no. 3, pp. 9-13, Summer 2017.
[82] L. Kull et al., "28.5 A 10b 1.5GS/s pipelined-SAR ADC with background second-stage common-mode regulation and offset calibration in 14nm CMOS FinFET," 2017 IEEE International Solid-State Circuits Conference (ISSCC), 2017, pp. 474-475
[83] L. Luo et al., "A 0.014mm2 10-bit 2GS/s time-interleaved SAR ADC with low-complexity background timing skew calibration," 2017 Symposium on VLSI Circuits, 2017, pp. C278-C279.