本論文可分為兩個部分，第一部分為可切換式2.4-和5-GHz雙頻接收機前端電路設計為低雜訊放大器與混頻器之整合；第二部分為3.6~4.3 GHz非整數型鎖相迴路電路設計。上述電路操作電壓皆為1.8 V，且使用TSMC 0.18 μm CMOS製程實現。
可切換式2.4-和5-GHz雙頻接收機前端電路主要電路架構為兩級寬頻低雜訊放大器串接雙頻切換式混頻器。寬頻低雜訊放大器擁有較低的雜訊指數，透過串接兩級低雜訊放大器提高增益同時降低後級混頻器所提供之雜訊指數，增加整體接收機的靈敏度；雙頻切換式混頻器採用切換輸入匹配達到雙頻的目標，加上電流再利用注入式混頻器可提供較高的轉換效率與轉換增益。可切換式2.4-和5-GHz雙頻接收機前端電路可將2.4-及5-GHz的輸入訊號降頻至1500 MHz輸出訊號，量測結果在2.4 GHz模式下，整體轉換增益為22.7 dB；雜訊指數為3.79 dB；P1dB為-37 dBm；IIP3為-27 dBm；功率消耗為36.306 mW，在5 GHz模式下，整體轉換增益為14.4 dB；雜訊指數為4.71 dB；P1dB為-29.5 dBm；IIP3為-20 dBm；功率消耗為36.31 mW。
在3.6~4.3 GHz非整數型鎖相迴路電路設計中，包含了相位頻率偵測器(PFD)、充電泵(Charge Pump)、迴路濾波器(Loop Filter)、環形壓控振盪器(Ring-VCO)、多模數除頻器(Multi-Modulus Divider)和三級三角積分調變器(Sigma Delta Modulator)之設計及整合。在非整數型鎖相迴路量測上，輸入參考訊號為40 MHz弦波，其操作頻率為3.62 GHz至4.32 GHz；輸出功率皆大於-12.2 dBm；相位雜訊在1 MHz偏移處皆低於-83 dBc/Hz，在10 MHz偏移處皆低於-100 dBc/Hz；功率消耗為87.2 mW。
上述電路設計未來希望藉由雙頻單通道較小面積的特色，應用於物聯網感測晶片與WLAN晶片，以因應目前產品間龐大的訊息傳輸，所需要的通訊硬體提升。

This thesis presents the design of switchable 2.4-/5-GHz dual-band receiver front-end circuits and 3.6~4.3 GHz fractional-N PLL. The operating voltages of the above circuits are all 1.8 V, and fabricated in TSMC 0.18 μm CMOS process.
Both the circuit structures of the 2.4-GHz and 5-GHz dual-band receiver front-end circuits consist two wideband LNA stages connected in cascade with a dual-band switchable mixer. The two wideband LNA stages provides low noise figure (NF) and high gain, to reduce the nosie figure effect provided by the post-stage circuits, thereby increasing the overall receiver sensitivity. The dual-band switchable mixer adopts switchable input impedance to achieve dual frequency mode, and the current-reused bleeding technique can provide better conversion efficiency and conversion gain. The 2.4-GHz and 5-GHz dual-band receiver front-end circuit can down-convert both 2.4-GHz and 5-GHz input signals to 1500 MHz output signal. In the 2.4 GHz mode, the overall measured conversion gain is 22.7 dB; the noise figure is 3.79 dB; P1dB is -37 dBm and IIP3 is -27 dBm. The total power consumption is 36.306 mW. In the 5 GHz mode, the overall measured conversion gain is 14.4 dB; noise figure is 4.71 dB; P1dB is -29.5 dBm and IIP3 is -20 dBm. The total power consumption is 36.31 mW.
The 3.6~4.3 GHz fractional-N PLL design includes a phase frequency detector, a charge pump, a loop filter, a ring voltage-controlled oscillator, a multi-modulus divider and a delta-sigma modulator. For the measurement of fractional-N PLL, input reference signal is set as 40 MHz sine wave. The PLL frequency tuning range is from 3.62 GHz to 4.32 GHz, and the overall measured output power is greater than -12.2 dBm; the phase noise is greater than 83 dBc/Hz at 1 MHz offset, greater than -100 dBc/Hz at 10 MHz offset, total power consumption is 87.2 mW.

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