| 研究生: |
曾英忠 Zeng, Ying-Jhong |
|---|---|
| 論文名稱: |
適用於H.264之高輸出率CABAC編碼器設計與測試 Design and Test of a High-Throughput CABAC Encoder for H.264 |
| 指導教授: |
謝明得
Shieh, Ming-Der |
| 學位類別: |
碩士 Master |
| 系所名稱: |
電機資訊學院 - 電機工程學系 Department of Electrical Engineering |
| 論文出版年: | 2006 |
| 畢業學年度: | 94 |
| 語文別: | 英文 |
| 論文頁數: | 93 |
| 中文關鍵詞: | 內容適應性二位元算術編碼器 、語法結構元素 |
| 外文關鍵詞: | CABAC Encoder, Syntax Element |
| 相關次數: | 點閱:101 下載:2 |
| 分享至: |
| 查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報 |
由於內容適應性二位元算術編碼器所需處理的資料是含括各個種類的語法結構元素,且因其本身具有資料相依之問題,若欲於每個時脈週期固定處理兩筆經由二位元轉換器所產生的輸入時,整體控制複雜度將會大幅增加。在本論文中,我們提出如何藉由分析不同的視訊資料經過二位元轉換器所產生的資料量分布狀況,以及僅針對某些特定語法結構元素才採用每一時脈週期處理兩筆經轉換資料之處理方式,來達到付出極少硬體成本就可明顯改善輸出率的目標。同時,我們也探討如何經由記憶體排列方式與其他技巧來提升工作頻率並減少後段所需之測試時間。從實現結果以及實驗數據可以明顯看出所提之內容適應性二位元算術編碼器設計以及所採用的測試技術所得到之優勢。
Because CABAC deals with various types of syntax elements and the inherent data dependency problems exist in the encoding process, it will result in dramatically increased controller complexity if two bins obtained from binarizing any syntax element are handled per clock cycle. In this work, by analyzing the distribution of binarized bins among different video sequences and only allowing a certain type of syntax elements to be processed two bins at a time, we show that significant throughput improvement can be achieved with very limited hardware overhead. In the meanwhile, we also describe the employed memory arrangement scheme and present techniques to improve the operating frequency and the test application time of our design. Experimental results exhibit the advantages of employing the developed design and test schemes.
[1]A. Tamhankar and K.R. Rao, "An overview of H.264/MPEG-4 Part 10," Video/Image Processing and Multimedia Communications, pp. 1-51, 2003.
[2]I.E.G. Richardson, H.264 and MPEG-4 Video Compression, Video Coding for Next-generation Multimedia. 2003
[3]H. Shojania and S. Sudharsanan, "A high performance CABAC encoder," in Proc. IEEE-NEWCAS Conference, pp. 315 - 318, June 2005.
[4]R.R. Osorio and J.D. Bruguera, "Arithmetic coding architecture for H.264/AVC CABAC compression system," in Proc. Euromicro Symposium on Digital System Design, pp. 62 - 69, Sept. 2004.
[5]R.R. Osorio and J.D. Bruguera, "A new architecture for fast arithmetic coding in H.264 advanced video coder," in Proc. Euromicro Conference on Digital System Design, pp. 298-305, Sept. 2005.
[6]M.D. Shieh, S.C. Shen, Y.C. Lin, and K.J. Lee, "Efficient testing and design-for-testability schemes for multimedia cores: a case study on DCT circuits," in Proc. APCCAS, pp. 177 - 180, Dec. 2004.
[7]W.P. Marnane and W.R. Moore, "Testing a motion estimator array," in Proc. Application Specific Array Processors Conference, pp. 734 - 745, 1990.
[8]L. Wall, K. Ferens, and W. Kinsner, "Real-time dynamic arithmetic coding for low bit-rate channels," in Proc. IEEE Communications, Computers and Power Conference, pp. 381 - 391, May 1993.
[9]V. Bhaskaran and K. Konstantinides, Image and Video Compression Standards Algorithms and Architectures.1997
[10]I.H. Witten, R. M. Neal and J. G. Cleary, "Arithmetic coding for data compression," Cpmmun. ACMm vol. 30, no. 6, pp. 520 -540, June 1987.
[11]P.G. Howard and J.S. Vitter, "Arithmetic coding for data compression," Proceedings of the IEEE, pp. 857 - 865, June 1994.
[12]G.G. Langdon and J.J. Rissanen, "Compression of black-white images with arithmetic coding," IEEE Trans. Commun. COM-29, pp. 858 - 867, June 1981.
[13]W.B. Pennebaker, J.L. Mitchell, G.G. Langdon, Jr. and R.B. Arps, "An overview of the basic principles of the Q-Coder adaptive binary arithmetic coder," IBM J. RES. DEVELOP. vol. 32 no. 6, pp. 717 - 726, Nov. 1988.
[14]D. Marpe, H. Schwarz, and T. Wiegand, "Context-based adaptive binary arithmetic coding in the H.264/AVC video compression standard," IEEE Trans. CAS for Video Technology, pp. 620 - 636, July 2003.
[15]ITU-T Rec. H.264 (03/2005).
[16]J.W. Chen, C.R. Chang, and Y.L. Lin, "A hardware accelerator for context-based adaptive binary arithmetic decoding in H.264/AVC," in Proc. IEEE International Symposium on Circuits and Systems, pp. 4525 - 4528, May 2005.
[17]C.-A. Chen and S.K. Gupta, "Efficient BIST TPG design and test set compaction via input reduction," IEEE Trans. on Computer-aided Design on Circuits and Systems, pp. 692 - 705, Aug. 1998.
[18]J.-J. Chen, Test Application Time and Power Reduction Techniques for Scan-Based Circuits, Dissertation, National Cheng-Kung University, Taiwan, 2003
[19]C.-M. Ho, Novel Scan Techniques for Low Power and Low Cost Testing, Master thesis, National Cheng-Kung University, Taiwan, 2003
[20]K. Miyase, S. Kajihara, and S.M. Reddy, "Multiple scan tree design with test vector modification," in Proc. Asian Test Symposium, pp. 76 - 81, Nov. 2004.
[21]C.-W. Wu and P.R. Cappello, "Easily testable iterative logic arrays," IEEE Trans. on Computers, pp. 640 - 652, May 1990.
[22]S.-K. Lu, J.-S. Shih and S.-C. Huang, "Design-for-testability and fault-tolerant techniques for FFT processors," IEEE Trans. on VLSI Systems, pp. 732 - 741, June 2005.
[23]S.-K. Lu, C.-W. Wu, and S.-Y. Juo, "Design of easily testable VLSI arrays for discrete cosine transform," in Proc. Asilomar Conference on Signals, Systems and Computers, pp. 989 - 993, Oct. 1992.
[24]M. Gala, D. Ross, K. Watson, B. Vasudevan, and P. Utama, "Built-in self test for C-testable ILA's," IEEE Trans. on Computer-aided Design on Integrated Circuits and Systems, pp. 1388 - 1398, Nov. 1995.
[25]K.-J. Lee, J.-J. Chen and C.-H. Huang, "Broadcasting test patterns to multiple circuits," IEEE Trans. on Computer-aided Design on Integrated Circuits and Systems, pp. 1793 - 1802, Dec. 1999.