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研究生：	曾懷寬 Zeng, Huai Kuan
論文名稱：	獨立雙閘極鰭式電晶體快閃記憶體之TCAD模擬 Modeling and simulation of independent double gate FinFET flash memory
指導教授：	盧達生 Lu, Darsen
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2018
畢業學年度：	106
語文別：	中文
論文頁數：	50
中文關鍵詞：	雙閘極、快閃記憶體、氧化物-氮化物-氧化物（ONO）
外文關鍵詞：	Double Gate, Flash Memory, Oxide - Nitride - Oxide (ONO)
相關次數：	點閱：122 下載：2
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隨著科技技術不斷進步，人們對於電子產品的要求逐漸提升，因此半導體產業也不斷地在蓬勃發展，而為了滿足電子產品對記憶體的需求，如使其縮小化、低功率消耗、增大記憶體容量及提高讀取速度……等等，尤其是現代AI是代的來臨，因此發展更高能性的記憶體，對於現在的科技產業業就顯得相當重要。然而因遵循著Moore’s Law的規範，隨著技術節點不斷降低，在元件物理特性及製程上面臨極限的問題。
本篇論文主要是透過利用Sentaurus TCAD軟體建構並分析在獨立雙閘極FinFET快閃記憶體的元件特性。眾所周知，利用3DFinFET通道器件可提供出色的短通道效應（SCE）抵抗度。因此，開發具有氧化物 - 氮化物 - 氧化物（ONO）電荷俘獲層的3D通道FinFET閃存記憶體。而獨立雙閘極FinFET閃存記憶體比起傳統的SONOS閃存記憶體，又具有以下的優點：可藉由兩條wordline控制兩個電荷俘獲層，使其達到能儲存2個bit。

Memory requirements for electronic products include narrow size, low power consumption, high memory capacity, and high read speed. The development of high-performance memory is very important for the technology industry.
This dissertation focuses on the construction and analysis of the component characteristics of independent double-gate FinFET flash memory using Sentaurus TCAD software. Using three-dimensional (3D) FinFET channel devices can provide a excellent short channel effect. Thus, scaled 3D channel FinFET flash memory with oxide-nitride-oxide charge trapping layers have been actively developed. Independent double-gate FinFET flash memory has the following advantage over conventional silicon–oxide–nitride–oxide–silicon flash memory: two charge-trapping layers can be controlled by two word lines so that two bits can be stored.

 CONTENTS
中文摘要	i
Abstract	ii
Acknowledgement	iii
LIST OF FIGURES	vi
LIST OF TABLES	ix
Chapter 1. Introduction	1
1.1 Foreword	1
1.2 Applications and problems of flash memory	1
1.3 Research purpose and motivation	2
Chapter 2. Introduction and mechanism	4
2.1 Introduction to memory	4
2.1.1 Floating gate structure	7
2.1.2 SONOS structure：	8
2.2 Physical mechanism of memory	11
2.2.1 Hot election injection	11
2.2.2 Tunneling	12
Chapter 3. Simulation and analysis	14
3.1 Experiment introduction	14
3.2 Physical mechanism model	16
3.2.1 Shockley-Read-Hall model	16
3.2.2 Non-local tunneling model	17
3.2.3 Threshold voltage extraction model	19
3.3 Single-gate FinFET model	20
3.3.1 Simulation component structure and parameters	20
3.3.2 Simulation results	22
3.4 Independent double-gate model	25
3.4.1 Simulation component structure and parameters	25
3.4.2 Simulation results	26
3.5 Oral committee question	33
Chapter 4.  Conclusions and future development	37
Appendix	38
Reference	48
LIST OF FIGURES
Figure 1.1 Schematic diagram of 3D NAND array.	2
Figure 2.1 (a) NOR connection	6
Figure 2.1 (b) NAND connection	6
Figure 2.2(a) Floating gate structure.	9
Figure 2.2(b) SONOS structure.	10
Figure 2.3 Band diagram of floating-gate flash memory during charge saving	10
Figure 2.4 Band diagram of SONOS flash memory during charge saving	11
Figure 2.5 In MOS, hot carriers are injected into oxide layer	12
Figure 2.6(a) Direct tunneling energy band diagram	13
Figure 2.6(b) Fowler-Nordheim tunneling energy band diagram	13
Figure 3.1 Normal FinFET Flash memory transistor layout diagram.	14
Figure 3.2 Independent double-gate FinFET flash memory transistor layout diagram.	15
Figure 3.3 Four processes of electron-hole recombination	17
Figure 3.4 eBarrier tunneling and hBarrier tunneling.[14]	18
Figure 3.5 Non-local parameter settings.	19
Figure 3.6 Threshold voltage extraction parameter settings.	20
Figure 3.7 Single-gate FinFET flash memory.	21
Figure 3.8 Number of electrons in storage layer after writing.	23
Figure 3.9 Threshold voltage vs. program time.	24
Figure 3.10 Threshold voltage vs. erasing time.	24
Figure 3.11 I-V curves from TCAD simulation write and erase.	25
Figure 3.12 Independent double-gate FinFET flash memory	26
Figure 3.13 Program time vs. back gate Vt.	29
Figure 3.14 Program voltage vs. back gate Vt of front gate and back gate.	29
Figure 3.15 Program voltage vs. ∆Vt of front gate and back gate.	30
Figure 3.16 Program voltage vs. storage eDensity of front gate and back gate.	30
Figure 3.17 Depletion for doping concentration of 2 x 1018.	31
Figure 3.18 Depletion for doping concentration of 1 x 1019	31
Figure 3.19 Program voltage vs. Vt of front gate and back gate for     doping concentration of 1 x 1019.	32
Figure 3.20 Program voltage vs. ∆Vt of front gate and back gate for   doping concentration of 1 x 1019.	32
Figure 3.21 Depletion for N doping	33
Figure 3.22 Depletion for doping concentration of 4 x 1018.	34
Figure 3.23 Depletion for doping concentration of 6 x 1018.	35
Figure 3.24 Depletion for doping concentration of 8 x 1018.	35
Figure 3.25 Depletion for doping concentration of 2 x 1019.	36
LIST OF TABLES
Table 2.1 Comparison between NOR and NAND flash memory.	7
Table 3.1 parameters for FinFET flash memory model.	21


                                    

[1] Hwang, J.-R., et al. 20nm gate bulk-FinFET SONOS flash. Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International, IEEE.
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[3] Park, Ki-Tae, et al. "Three-dimensional 128 Gb MLC vertical NAND flash memory with 24-WL stacked layers and 50 MB/s high-speed programming." IEEE Journal of Solid-State Circuits50.1 (2015): 204-213.
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http://wiki.csie.ncku.edu.tw/embedded/Flash#nornand-flash%E4%BB%8B%E7%B4%B9 ,(2018/06/12)
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[6]” Floating Gates and Electron Tunnels: Flash Retains Data”, http://dataonfire.com/blog/2015/02/floating-gates-and-electron-tunnels-flash-retains-data/ , (2018/06/01)
[7] Min She, ”Semiconductor Flash Memory Scaling” (2003)
[8] Shiyanovskii, Yuriy, et al. "Hardware Trojan by hot carrier injection." arXiv preprint arXiv:0906.3832 (2009).

[9] Roy, Kaushik, Saibal Mukhopadhyay, and Hamid Mahmoodi-Meimand. "Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits." Proceedings of the IEEE 91.2 (2003): 305-327.
[10] Jitu J. Makwana, Dr. Dieter K. Schroder "A Nonvolatile Memory Overview"
http://aplawrence.com/Makwana/nonvolmem.html , (2018/06/01)
[11] Tsung-Han Lu, "Reliability of Devices in NAND Flash Memory Periphery Circuitry"國立成功大學碩士論文,2013
[12] Lai, Stefan. "Tunnel oxide and ETOX/sup TM/flash scaling limitation." Nonvolatile Memory Technology Conference, 1998. 1998 Proceedings. Seventh Biennial IEEE. IEEE, 1998.
[13] Biswas, Arnab, et al. "TCAD simulation of SOI TFETs and calibration of non-local band-to-band tunneling model." Microelectronic Engineering 98 (2012): 334-337.
[14] "Sentaurus™ Device User Guide" Version L-2016.03, March 2016, Synopsys, Inc.
[15] Darsen D. Lu, "Stressor Design for FinFETs with Air-Gap Spacers." Electrical Engineering, IEEE.

[16]Ying–Tsai Ting, "Study on Operation and Structure of SONOS Type Flash Device"國立清華大學碩士論文,2009
[17] Sung, Suk-Kang, et al. "Fully integrated SONOS flash memory cell array with BT (body tied)-FinFET structure." IEEE transactions on nanotechnology 5.3 (2006): 174-179.
[18] Goudon, Thierry, Vera Miljanović, and Christian Schmeiser. "On the Shockley–Read–Hall model: generation-recombination in semiconductors." SIAM Journal on Applied Mathematics 67.4 (2007): 1183-1201.

校內：2023-08-18公開
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