| 研究生: |
簡新恩 Jian, Shin-En |
|---|---|
| 論文名稱: |
結合晶片網路與匯流排之三維網狀架構之高效能無死鎖傳輸方法 An Efficient Deadlock-Free Communication Scheme for 3D NoC-Bus Hybrid Mesh Architecture |
| 指導教授: |
李昆忠
Lee, Kuen-Jong |
| 學位類別: |
碩士 Master |
| 系所名稱: |
電機資訊學院 - 電機工程學系 Department of Electrical Engineering |
| 論文出版年: | 2013 |
| 畢業學年度: | 101 |
| 語文別: | 英文 |
| 論文頁數: | 48 |
| 中文關鍵詞: | 結合晶片網路與匯流排之三維網狀架構 、無死鎖 、繞徑演算法 |
| 外文關鍵詞: | 3D NoC-bus hybrid mesh architecture, Deadlock-Free, Routing Algorithm |
| 相關次數: | 點閱:139 下載:0 |
| 分享至: |
| 查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報 |
三維晶片堆疊技術擁有較高傳輸效能及較低接線功率的優點,結合晶片網路與匯流排之三維網狀架構(3D NoC-bus hybrid mesh architecture)被提出來並且擁有這些優點。基於這個架構,我們提出了一個無死鎖(deadlock-free)繞徑方法,這個方法可以處理死鎖問題只需要使用一個虛擬通道在x方向以及兩個虛擬通道在y和z方向。我們進一步分析這個方法不同的結構並顯示其結構可以提升繞徑效率藉由在z方向在添加一個最小尺寸的虛擬通道。而且我們發展了一個完全適應(fully adaptive)路徑演算法,這個演算法考慮到鄰近匯流排的流量負載以及目前路由器輸出端口的可用性。我們也模擬各種實驗,包含不同的網路規模、虛擬通道內緩衝器容量、封包大小以及多種流量模式,並且設定多種封包發送頻率。結果顯示在所有這些實驗中,我們所提出來的繞徑方法效能都優於過去兩種繞徑方法,這兩種方法也是基於結合晶片網路與匯流排之三維網狀架構。
The three-dimensional integrated circuit (3D IC) stacking technology has the advantages of higher routing performance and lower interconnect power. The 3D NoC-bus hybrid mesh architecture is developed to take these advantages. Based on this architecture we propose a deadlock-free routing scheme that can deal with the deadlock problem using only one virtual channel (VC) in the x-direction and two virtual channels in both y- and z-directions. We further analyze a variant of this scheme and show that the routing efficiency can be further improved by adding a minimum-size VC at the z-direction. A fully adaptive routing algorithm is also developed which takes the traffic loads of neighbor buses and the availability of output ports of the current router into account. We have carried out experiments with different network dimensions, VC buffer sizes, packet sizes, and traffic patterns under various traffic injection rates and the results show that the proposed scheme outperforms previously developed routing schemes based on the 3D NoC-bus hybrid mesh architecture in all of these experiments.
[1] W.O. Cesário, D. Lyonnard, G. Nicolescu, Y. Paviot, S.Yoo, A.A. Jerraya, L. Gauthier, and M. Diaz-Nava, “Multiprocessor SoC platforms: a component-based design approach,” IEEE Design and Test of Computers, vol. 19, no. 6, pp. 52-63, 2002.
[2] B. S. Feero and P. P. Pande, “Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation,” IEEE Transactions on Computers, vol. 58, no. 1, pp. 32-45, 2009.
[3] J. Kim, C. Nicopoulos, D. Park, R. Das, Y. Xie, V. Narayanan, M. S. Yousif, and C. R. Das, “A novel dimensionally-decomposed router for on-chip communication in 3D architectures,” in Proc. of International Symposium on Computer Architectures, pp. 138-149, 2007.
[4] F. Li, C. Nicopoulos, T. Richardson, Y. Xie, V. Narayanan, and M. Kandemir, “Design and Management of 3D Chip Multiprocessors Using Network-in-Memory,” International Symposium on Computer Architecture, pp. 130-141, 2006.
[5] A.-M. Rahmani, V. Kameswar Rao, K. Latif, P. Liljeberg, J. Plosila, and H. Tenhunen, “High-Performance and Fault-Tolerant 3D NoC-Bus Hybrid Architecture Using ARB-NET Based Adaptive Monitoring Platform,” accepted by IEEE Transactions on Computers.
[6] L. P. Carloni, P. Pande, and Y. Xie, “Networks-on-Chip in Emerging Interconnect Paradigms: Advantages and Challenges,” in Proc. of International Symposium on Networks-on-Chip, pp. 93-102, 2009.
[7] W.J. Dally, “Virtual-channel flow control,” IEEE Transactions on Parallel and Distributed Systems, vol. 3, no. 2, pp. 194-205, 1992.
[8] L. Ni and P. McKinley, “A survey of wormhole routing techniques in direct networks,” IEEE Computer, vol. 26, no. 2, pp. 62-76, 1993.
[9] D.H. Linder and J.C. Harden, “An Adaptive and Fault-Tolerant Wormhole Routing Strategy for k-Ary n-Cubes,” IEEE Transactions on Computers, vol. 40, no. 1, pp. 2-12, 1991.
[10] M. Li, Q.-A. Zeng, and W.-B. Jone, “DyXY: a proximity congestion-aware deadlock-free dynamic routing method for network on chip,” Design Automation Conference, pp. 849-852, 2006.
[11] C. J. Glass and L. M. Ni, “Maximally fully adaptive routing in 2D meshes,” International Conference Parallel Processing, pp. 101-104, 1992.
[12] M. M. H. Rahman and S. Horiguchi, “High performance hierarchical torus network under matrix transpose traffic patterns,” International Symposium on Parallel Architectures, Algorithms and Networks, pp. 111-116, 2004.
[13] C. J. Glass and L. M. Ni, “The turn model for adaptive routing,” Journal of ACM, pp. 278-287 1994.
[14] G.-M. Chiu, “The odd-even turn model for adaptive routing,” IEEE Transactions on Parallel and Distributed Systems, vol. 11, no. 7, pp. 729-738, 2000.