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研究生：	孫廷瑋 Sun, Ting-Wei
論文名稱：	具有單向時脈控制之低功率八位元每秒二百五十萬次取樣快閃式類比/數位轉換器 A Low-Power 8-Bit 250MS/s Flash A/D Converter with Single Phase Clock Control
指導教授：	郭泰豪 Kuo, Tai-Haur
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2006
畢業學年度：	94
語文別：	英文
論文頁數：	94
中文關鍵詞：	平均、葛雷碼、前置放大器、內插、類比數位轉換器、追蹤與保持電路、快閃式類比數位轉換器、比較器
外文關鍵詞：	Track-and-Hold, Preamplifier, Averaging, Analog-to-Digital Converter, Comparator, Gray Code, Flash Converter, Interpolation.
相關次數：	點閱：82 下載：3
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由於製程技術的進步，CMOS 積體電路的操作頻率及電路複雜度也隨著增加。介於類比與數位之間的介面需要極高速的操作速度，約是每秒幾百萬次取樣到每秒幾億次取樣不等。這些高傳輸率的系統，包含DVD 讀取通道、多準位接收器、通道等化器、時脈抖動量測系統或乙太網路都需要類比數位轉換器。在這篇論文中包含了兩個主題。首先，我們將焦點放在高速類比數位轉換器的電路設計方法，接下來是快閃式類比數位轉換器的實作。因此我們提出一個在一般能操作250MHz工作頻率以及解析度為八位元快閃式類比數位轉換器。在此論文中我們使用許多常在類比數位轉換器所見的設計技巧和電路並改良其原本設計。因此，此類比數位轉換器可以操作在如此高速的取樣頻率。在最前端我們使用了一個新設計的切換式前置放大器，因此可以使用單一相位時脈就可以控制此快閃式類比數位轉換器。另外，在此快閃式類比數位轉換器中我們使用了自動歸零技巧，電容的平均化技術以減少最前端切換式前置放大器所造成的偏移誤差，以及在比較器陣列裡面所使用的內插技巧以減少比較器的使用數量。使用這些技巧，可以大大的降低存在類比數位轉換器內部所造成的誤差。因此使此設計可以有更好的效能。此外，為了改善動態表現，在前置放大器之前加入一個追蹤保持電路。在數位解碼方面，使用了三端輸入的或閘以及灰階編碼的唯讀記憶體。用來降低因為氣泡效應與比較器陣列的亞穩態(metastability)所造成的轉換錯誤。此晶片實現是採用0.18μm，1P6M互補金氧半混合信號製程，面積為1.37×1.19mm2。量測結果證實此類比數位轉換器在輸入信號為122.07MHz，取樣頻率為250MHz時，具有44.19dB SNDR的動態表現，即7.42的有效位元。此晶片在1.8V的供應電壓下，消耗137mW的功率。與目前全世界已發表最好的快閃式類比數位轉換器，此設計具有較小面積，及消耗功率。

Due to the advance process technologies, the operating frequency and circuit complexity of integrated circuit increase. The interfaces between the analog and the digital parts are required to operate at ultra high speed (over giga samples per second). The high-bit-rate applications include DVD read channel, multi level receiver, channel equalizer, jitter measurement system, and Ethernet need Analog-to-Digital Converters. There are two major topics in this thesis. First, we focus on the design technique of high speed ADC. On the next is the design actual circuit of Flash analog to digital converter. Thus we propose a sampling frequency at 250MHz and resolution 8 bits flash analog to digital converter. In this thesis we use many design technique and circuit often seen in the design of analog to digital converter and improve the disadvantage of original technique and circuit. Thus this analog to digital converter can operate at such high sampling frequency. In the front of comparator array we used a switching preamplifier circuit. Thus we can use single phase to control this analog to digital converter. Besides, we use the autozeroing combine capacitor averaging and reinterpolation technique in order to reduce the offset in the switching preamplifier. In the comparator array, we use the interpolation technique the reduce the number of preamplifier. By using these technique, we can have great reduce the offset error in analog to digital converter, thus this design can have better performance. In order to improve the dynamic performance of this flash ADC, we add a track and hold circuit in front of the preamplifier array. In digital encoder design, we use a three-input NAND gate combines Gray-coded ROM, used to reduce the error code caused by bubble error or comparator metastability.
The ADC is fabricated in 0.18μm 1P6M CMOS technology and occupies an area of 1.37x1.19mm2. The measurement results demonstrate that the ADC can digitize an input 122.07 MHz with 44.19dB SNDR, which means 7.42 ENOB at 250MS/s. The ADC consumes 137mW from 1.8V power supply. Compared with the best CMOS flash ADC in the world, this design has smaller, low supply voltage, and less power.

Chapter 1. Introduction 1
1 Background 1
2 Motivation 1
3 Thesis organization  3
Chapter 2. Fundamentals of Analog to Digital Converter  4
1 Basic Concepts .4
1.1 Introduction of Analog to Digital Converters  5
1.2 Aliasing Effect 7
1.3 Ideal Analog to Digital Converter .8
2 Some Error Source in Analog to Digital Converter 8
2.1 Quantization Error .8
2.2 The Distortion in MOS Differential Pair 10
2.2.1 Computation harmonic from DC transfer characteristic 11
2.3 Metastability Error 13
2.3.1 Operation Time of Simply Latch 13
2.3.2 Metastability Error and Probability 14
3 Specifications .16
3.1 Static Specifications 16
3.2 Dynamic Specifications 18
4 Analog to Digital Converter Architectures 19
5 Flash Analog to Digital Converter  20

Chapter 3. System Level Design of the Flash ADC 22
1 Averaging Technique 22
2 Interpolation Technique 23
3 Autozeroing Technique 25
3.1 Some Problem in Traditional Autozeroing Technique 26
4 The Autozeroing with Single Phase Control  27
5 Track and Hold Technique 28
5.1 Basic Track and Hold configuration 29
4.1.1 Close and Open Loop 29
4.1.2 Signal Bandwidth 29
4.1.3 Acquisition time 30
5.2 Some Error of Track and Hold Technique 30
4.2.1 Sampling-Time Uncertainly 30
4.2.2 Thermo Noise 32
4.2.3 Nonlinearity 32
6 Comparison of Differential Design Techniques 33
6.1 8-bit Flash Analog to Digital Converter with Auto-zero
         Technique 33
6.2 8-bit Flash Analog to Digital Converter with Auto-zero combine with
         Track and Hold Technique 34
6.3 8-bit Flash Analog to Digital Converter with Distributed Track and
         Hold and Resistive Interpolation 35
6.4 8-bit Flash Analog to Digital Converter with Resistive Averaging 36
7 Some High Speed Flash Analog to Digital Converter Architecture in Real
     Application 37
7.1 4-bit 4-G Flash Architecture 37
7.2 5-bit 5-G Flash Architecture Using Active Interpolation Technique 38
7.3 5-bit 4-G Flash Architecture Using Averaging Technique 39
8 The Design Issues and Architecture of High Speed Flash Analog to Digital
      Converter in This Thesis 40
8.1 Design Guidelines  41
8.2 Design Technique in This Technique 41

Chapter 4. Circuit Level Design of the Flash ADC 44
1 Low Voltage CMOS Design Technique 44
1.1 Process Considerations 44
1.2 Low Voltage and Low Power Concerns 45
1.3 Device Matching .46
1.4 Passive Components 47
1.5 Analog Circuits in a Digital Environment .47
1.6 Methodology for Low Power Circuit Design 48
2 The Architecture of This Flash Analog to Digital Converter 49
3 Track-and-hold Circuit 50
4 Comparator Circuit Design 55
4.1 Switching Preamplifier Circuit 55
4.1.1 The Operation of Switching Preamplifier 55
4.1.2 The Layout Consideration of Switching Preamplifier 57
4.2 Second and Third Stage Preamplifier 58
4.2.1 Second Stage Preamplifier 58
4.2.2 The Gain of Second Stage Preamplifier 60
4.2.3 Third Stage Preamplifier 61
5 Latch Circuit Design. 62
5.1 The Amplifier Phase of Latch Circuit .62
5.2 The Analysis of the Switch 64
5.3 The Operation of the Latch .65
6 Control Signal of Preamplifier Array 67
7 Digital Encoder Circuit Design 68
7.1 ROM Based or Digital Logic Gate Based?  69
7.2 Implement the Digital Encoder Circuit 69
8 Bias Circui 71
9 Clock Generator Circuit 72

Chapter 5. Chip Design and Measurement Result 74
1 Layout Consideration 74
1.1 Power Supply Partition 74
1.2 Layout Technique 75
2 Simulation Considerations 78
3 Simulation Result 78
4 Measurement Setut 82
5 The Design Consideration of PCB Board .83
5.1 Transmission Line Effect 83
5.2 Cross Talk  84
5.3 Decoupling 84
6 PCB Fabrication 84
7 Experimental Result  85
Chapter 6. Conclusion and Future Work 88
References 91
                                    

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37.許浚偉：『具新自動歸零與內插有負阻抗補償之快閃類比/數位轉換器』中華民國發明專利已核准，申請案號91118051
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校內：2010-08-29公開
校外：2014-08-29公開

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