我們提出了一個可重新配置與虛擬化之類神經網路加速處理器，並且介紹了其硬體架構、軟硬體的溝通與硬體的虛擬化機制。我們提出的硬體架構能讓各種不同拓樸的類神經網路應用可以透過此硬體加速，其中包含了多層感知器類神經網路與霍普菲爾網路。倒傳遞演算法為最常見且實用的多層感知器類神經網路學習演算法。但倒傳遞演算法的網路訓練過程可能會耗費許多的時間，而若用硬體來平行處理作加速又會遇到記憶體存取的瓶頸造成效能不佳。為此我們提出一種存放類神經網路權重值的記憶體排列方式來消除記憶體存取的瓶頸，以此增進在硬體上處理倒傳遞演算法加速的效能。
此外，我們提出了一個建立在CASL hypervisor上綜合虛擬硬體與直接存取的虛擬化架構，在此虛擬化架構下可讓此類神經網路加速處理器達到效能的平衡且不影響整體效能。最後，我們在硬體上增加了輔助虛擬化所需的單元，使hypervisor 能夠公平且有效率的控管硬體資源。

In this thesis, we present a reconfigurable and virtualizable neural net processor, and introduce the hardware architecture, software-hardware co-design, and the device virtualization mechanism. The proposed hardware architecture is reconfigurable to accommodate several different neural network topologies and applications of MLP and Hopfield network in a single chip. To eliminate the memory bottleneck of error-backpropagation neural network training algorithm, we propose a weight memory management method to interleave the memory access order, and it improves the performance of on-chip training.
In addition, we propose a hybrid device-emulation and direct-access virtualization mechanism based on the CASL hypervisor to achieve low performance overhead and workload balance among multiple virtual machines. With the dual-bank weight memory design and other hardware supports, the hypervisor can manage the hardware resource effectively and fairly.

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