成功大學博碩士論文系統

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研究生：	鍾明良 Chung, Ming-Liang
論文名稱：	一個相容於標準CMOS製程並具有靜態隨機存取記憶體介面的嵌入式動態隨機存取記憶體 An Embedded DRAM with SRAM Interface in Standard CMOS Process
指導教授：	張順志 Chang, Soon-Jyh
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2009
畢業學年度：	97
語文別：	英文
論文頁數：	79
中文關鍵詞：	嵌入式記憶體
外文關鍵詞：	1T-SRAM, SRAM, DRAM, embedded memory
相關次數：	點閱：122 下載：6
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在本篇論文中我們提出一個操作於200MHz的嵌入式動態隨機存取記憶體. 此設計將動態隨機存取記憶體中的週期性更新操作隱藏執行, 並使其具有靜態隨機存取記憶體的操作介面, 因此其可視為一個兼具動態隨機存取記憶體(小面積)與靜態隨機存取記憶體(高操作速度)優點之嵌入式記憶體. 此嵌入式記憶體相容於一般CMOS標準製程, 不需額外光罩或是特殊製程步驟, 因此能降低製造成本.
此嵌入式記憶體中的記憶體區塊使用中芯0.16微米標準製程實現. 由晶片量測結果顯示資料維持時間可達5毫秒以上, 每一個記憶體區塊的平均消耗功率約為10.25毫瓦. 此外, 針對晶片量測結果所發現的問題, 我們提出新的記憶體單元及感應放大器架構來加以修正. 最新的設計除了能夠增加讀取穩定度外, 亦能有效地降低記憶體單元面積達傳統6T-SRAM的一半.

This thesis proposes a 200-MHz embedded dynamic random access memory (DRAM). The presented design hides the periodically refresh operation in background and provides static random access memory (SRAM) interface such that it has both of the advantages of DRAM (small cell area) and SRAM (fast operation speed). The proposed embedded memory is designed based on standard CMOS processes without additional special process steps.
The DRAM bank has been fabricated in SMIC standard 0.16-m 1P5M CMOS process. Measurement results show that the data retention time is over 5 milliseconds and the average power consumption of the memory bank is 10.25 mW. Moreover, a novel memory cell and a modified sense amplifier architecture are also proposed to solve the problems we met in the first design. The modified design increases the read stability and substantially decreases the cell area to only half of the conventional 6T-SRAM.

List of Figures vi
List of Tables ix
Chapter 1 Introduction 1
1 Motivation 1
2 Conventional Embedded Memory 2
2.1 Introduction to SRAM and DRAM 4
2.2 Blocks of Memory Architecture 7
3 Thesis Organization 14
Chapter 2 Cell Characterization 15
1 Design Consideration 15
2 Memory Cell Design 17
3 Simulation and Measurement Results of Cell Characteristics 19
Chapter 3 Proposed Embedded Memory Design 24
1 DRAM Core with SRAM Interface 24
2 Memory Bank Architecture 25
2.1 Cell with MOS Capacitor 26
2.2 Folded and Twisted Array Architecture 27
2.3 Row Decoder with Predecoding Scheme 28
2.4 Sense Amplifier and Precharge Circuit 29
2.5 Bank Control Logic 33
2.6 Access Collision Policy 34
2.7 Refresh Address Counter 35
2.8 Peripheral Circuits 36
3 Hiding Refresh Scheme 36
3.1 Data and Tag Cache 39
3.2 Hit or Miss Condition 40
3.3 Refresh Timer 43
4 Area Efficiency 43
5 Simulation and Measurement Results 45
5.1 Simulation Results 48
5.2 Measurement Consideration 53
5.3 Function Test 54
5.4 Retention Test 59
5.5 Summary 60
Chapter 4 Embedded Memory Design with Differential Sensing Scheme 62
1 Differential Sensing Scheme 62
2 Novel Memory Cell 63
3 Sense Amplifier with Preamp Scheme 65
4 Simulation Results 68
4.1 Data Retention Time 68
4.2 Signal Swing 69
4.3 Access Disturbance 71
4.4 Read Operation with Monte Carlo Simulation 72
5 Summary 73
Chapter 5 Conclusion and Future Work 74
1 Conclusion 74
2 Future Work 75
Bibliography 76
                                    

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校內：2014-07-31公開
校外：2014-07-31公開

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