由於製程技術持續地進步，單位面積中能整合的電晶體數目越來越多，這意味著電路設計者得以在同樣的面積中設計邏輯閘數目更多且功能更為強大的電路系統。為了增進大型電路系統的設計效率，設計者往往以矽智財來建立平台式設計，以於平台上實現所需的系統應用。在平台式設計中，矽智財之間資料的轉移與交換是影響整體系統效能最重要的因素之一。特別是在多核心系統中，多個處理核心往往需要大量的資料交換，這很有可能導致資料交換成為整體系統效能的瓶頸。因此，平台式設計中資料傳輸的晶片上傳輸架構，例如系統匯流排或網路晶片，就顯得格外重要。
平台式設計與晶片上傳輸架構相關之議題為數眾多，本論文針對其中三項與設計和測試相關之重要議題進行分析與探討，並進而提出相對之設計與解決方法。第一個議題與晶片上傳輸之介面與架構相關。先進的系統匯流排標準與介面標準僅定義傳輸系統的介面訊號與傳輸型態，而傳輸系統的電路架構則留予電路設計者自行設計，所以電路設計者較過去有更多的自由來決定採用共享式匯流排、多層次匯流排、縱橫匯流排或是網路晶片來實現資料交換的架構。因此，如何選擇高傳輸效率且兼具電路面積的晶片上傳輸架構之設計就顯得格外重要，此外若矽智財所採用的介面標準與晶片上傳輸架構採用的介面標準不同，亦會造成系統整合上的困難。在此論文中，我們針對先進之晶片上傳輸介面與傳輸型態來設計其傳輸架構，特別是能有效提升傳輸效率的亂序傳輸型態，使其能達到高傳輸效率。在我們的實驗結果中，相較於目前被廣泛使用的系統匯流排，我們僅須54%的面積就能提供相同的傳輸效率。此外我們亦提出能用以轉換不同先進介面標準的協定轉換器，以縮短系統整合所需的人力。
第二個議題為平台式系統單晶片之測試。在平台式系統單晶片中，許多矽智財電路皆深埋於系統晶片中而難以藉由晶片之外部接腳直接存取，導致測試時可控制性與可觀察性皆不足以達到高測試涵蓋率。目前已有許多研究提出能解決此問題的晶片上測試架構，然而這些測試架構所能提供的測試效率及其電路面積所造成的測試成本皆不盡相同。因此，如何有效地探索不同的測試架構進而提出能滿足所有測試需求且具最低測試成本的架構即為相當重要的議題。在此論文中，我們採用能有效幫助設計者解決系統層級議題的電子系統層級設計方法來解決系統單晶片之測試議題。我們首先提出系統層級的測試元件模型之設計，再利用這些測試元件模型快速地建立與模擬不同的測試架構，以達到測試架構探勘之目的。在我們的實驗結果中，相較於暫存器交換層級模型我們所提出的系統層級模型能加快模擬速度數千甚至數萬倍，而我們所提出的測試架構探勘方法亦能有效地尋找滿足測試需求且具最低測試成本的測試架構。
第三個議題為系統死結之議題。在支援亂序傳輸的系統匯流排中，我們可以透過資料的亂序回傳來達到較佳的傳輸效能。然而，亂序傳輸協定中仍存在著某些回傳順序的規範，這些規範可能會造成系統中一個傳輸等待另一個傳輸，當這樣的等待關係以一個循環的形式存在時，即造成系統死結。另外，在支援多目的地傳輸之網路晶片中，同樣可能因為封包的分支而造成數個封包間循環形式的等待，導致系統死結的發生。在此論文中，我們分別針對系統匯流排亂序傳輸之死結以及網路晶片中多目的地傳輸的死結問題進行分析與探討，並進而提出解決死結問題的方法及其電路。實驗結果證實我們的方法不但能有效地解決死結問題，而且還能提供較其他方法更高的傳輸效率。

As the VLSI process technology continues to advance, more and more transistors can be integrated into a chip, resulting in that designers can design systems with more logic gates and powerful functionalities. To increase the design efficiency of large and complexity systems, the platform-based design methodology that maps applications to components on a platform attract designers’ attention. In platform-based designs, data movement and transformation is of central importance. Especially in current designs that tend to integrate multiple processor cores into a system, data communication among these processor cores may become the bottleneck of overall system performance. Consequently, the on-chip communication architecture for data communication, such as on-chip buses or networks-on-chip, plays the key role in platform-based designs.
Plenty of issues are involved in on-chip communication and platform-based designs, and in this dissertation we focus on three essential and emerging ones. The first issue is design of on-chip buses and interface protocol converters. Some advanced communication protocols that facilitate parallel communications define communication interface and transaction types but leave communication architectures to designers. Designers thus have the freedom to implement the communication protocols using multi-layer, crossbar, networks-on-chip, or a combination of these designs to increase the communication parallelism. Consequently, designers of on-chip buses take more responsibility for overall system performance than usual. In addition, IP cores from different IP vendors may be wrapped with different interface protocols. As system integrators employ these IP cores to design an SOC system, they have to design adaptors or bridges to connect them to an in-house or public on-chip bus. Designing such adapters or bridges is not a difficult task, but the verification of the standard translation and compliance check is quite time consuming. In this dissertation, we propose an on-chip bus design for advanced communication protocols, especially the out-of-order facility, to achieve high communication efficiency. We also propose a protocol converter that translates different communication protocols to reduce effort of system integration. The experimental results show that the proposed bus design is quite efficient comparing with the most popular bus designers, and with our protocol converters IP cores are capable to be integrated with various bus systems.
The second issue is SOC testing. In platform-based SOC designs, many IP cores are embedded deeply, resulting in low controllability and observability. Lots of test architectures with various test parameters are proposed for SOC testing, resulting in various test performance and test cost. To evaluate test performance and test cost of these test architectures, we employ the Electronic System Level (ESL) design methodology that helps designers deal with system-level design issues to deal with test issues. We first propose transaction level models of test infra-structure and then construct the high-level test-structure to build the SOC test platform. With the advantages of the ESL design methodology, we can construct the SOC test platform with various parameters and simulate test procedures efficiently so as to explore the design space of the SOC test platform. Experimental results show that 3 to 4 orders of magnitude improvement on simulation speed can be achieved comparing with the RTL models, and the test time and area overhead of test architectures with various design parameters can be explored in just several minutes.
The third issue is about deadlocks. Out-of-order transactions that allow responses to be returned in an order different from their request order play an important role in communication improvement. However, a deadlock situation may occur if these transactions are not properly manipulated. Another scenario where a deadlock may occur is networks-on-chip supporting multicast routing. To deliver one packet to multiple destinations, packet duplication is efficient for communication. However, it may also cause deadlocks because circular hold-and-wait may occur among a set of duplicated packets. In this dissertation, we respectively analyze how a deadlock occurs in a bus supporting out-of-order transaction and in an NoC supporting multicast routing. We also respectively propose a method and its hardware implementation for deadlocks in the two scenarios. Experimental results show that the proposed methods avoid deadlocks and provide better communication efficiency than the previous work.

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