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研究生：	盧郁如 Lu, Yu-Ju
論文名稱：	運用放大器重置技術及切換式電阻電容技術之低壓高速管線式類比數位轉換器 A Low Voltage High Speed Pipelined Analog-to-Digital Converter Using Hybrid OPAMP-Reset Switching-Technique and Switched-RC Technique
指導教授：	劉濱達 Liu, Bin-Da
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2009
畢業學年度：	97
語文別：	英文
論文頁數：	81
中文關鍵詞：	放大器重置技術、切換式電阻電容技術、低電壓、管線式類比數位轉換器
外文關鍵詞：	pipelined ADC, OPAMP reset switching technique, switched-RC technique, low supply voltage design
相關次數：	點閱：127 下載：3
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本論文實現一個低電壓、高解析度、高速的管線式類比數位轉換器。為了解決浮動開關的問題，同時使用放大器重置技術以及切換式電阻電容技術，實現重置回授電容及電荷轉移的功能，進而達到高解析度的規格。針對低電壓、高速、高解析度的需求，我們使用的放大器為增強增益式折疊疊接放大器架構，比較器則為切換開關式架構。此外，為了使電路達到穩定，放大器的共模回授電路設計成可切換式，能在不同時脈下產生不同的輸出共模電壓。
本論文使用0.18 微米一層多晶矽六層金屬之互補式金氧半製程，實現一個供應電壓為1 伏特、輸出為10 位元的數位訊號、取樣頻率為50 百萬赫的管線式類比數位轉換器。在輸入訊號為2 百萬赫時，訊號對於雜訊及諧波失真比為 50.3分貝，整個電路的功率消耗為 33 毫瓦。

A low supply voltage, high resolution, and high speed pipelined analog-to-digital data convertor (ADC) is designed in this thesis. In order to solve the floating switch problem, hybrid OPAMP-reset switching-technique and switched-RC technique is used to implement the feedback capacitor reset and charge transfer functions for high
resolution requirement. To meet low supply voltage requirement, a gain-boosting folded-cascode operational amplifier (OPAMP) and a switched-capacitor comparator
are designed. For stability, a switchable common mode feedback (CMFB) circuit is designed to generate different output common mode voltages in each phase.
This pipelined ADC with 1-V supply voltage has been design in 0.18-μm CMOS process without low threshold MOS devices. The SNDR is 50.3 dB with the input frequency of 2 MHz and sample frequency of 50 MHz. The total power consumption
is 33 mW.

Abstract		
Acknolrgment	
Contents		
List of Tables	
List of Figures	
Chapter 1 Introduction	
1  Motivation	
2	Thesis Organization	
Chapter 2 Fundamentals of ADC	
1  Introduction to ADC	
1.1  Principle of ADC	
1.2  Concept of ADC	
1.3  Ideal ADC	
2  Specifications	
2.1  Static specifications	
2.2  Dynamic specifications	
3  Pipelined ADC Architecture	
3.1  Algorithm of pipelined ADC	
3.2  1.5-bit/stage pipelined ADC and digital correction
Chapter 3 Low Voltage Techniques of Pipelined ADC	
1  Clock Boosting	
2  Bootstrapped Switch	
3  Switched-OPAMP Technique	
4  OPAMP-Reset Switching-Technique (ORST)	
5  Switched-RC Technique	
Chapter 4 A 1-V 10-bit 50MS/s Pipelined ADC using Hybrid OPAMP-Reset Switching-Technique and Switched-RC Technique
1  Fully Differential ORST Multiplying Digital-to-Analog Circuit	
2  Track-and-Reset Circuit Design	
3  OPAMP Design	
3.1  Loading of OPAMP	
3.2  Specification of OPAMP	
3.3  Cascading folded-cascode OPAMP architecture	
3.4  Design issue of gain boosting	
3.5  Common mode feedback circuit	
4  Comparator Design	
5  1.5-bit Sub-ADC Design	
6  2-bit Flash ADC Design	
7  Digital Circuit Design	
7.1  Clock generator	
7.2  Digital error correction	
Chapter 5 Experimental Results	
1  Track-and-Reset Simulation	
2  OPAMP Simulation	
3  MDAC Simulation	
4  Two Bit Flash ADC Simulation	
5  Digital Circuit Simulation	
6  Overall Pipelined ADC Simulation	
Chapter 6 Conclusion	
1  Conclusions	
2  Future Work	
References
                                    

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校內：2010-08-11公開
校外：2010-08-11公開

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