對無線通訊系統而言，頻率合成器為相當重要之電路。而為了適用在不同的通訊系統規格應用，頻率合成器在頻段的規劃實現以及所要求的電路規格也有所不同。此論文中主要係針對一應用於MB-OFDM超寬頻系統之鎖相迴路進行設計。
此鎖相迴路操作頻率為6,336 MHz，輸入參考頻率為528 MHz。子電路中具變壓器共振腔之考畢茲壓控振盪器及真實單相時脈四相位除三電路為此電路主要特色。此外，此電路亦具有低功耗之特點。使用台積電所提供之雙端螺旋電感並利用線圈數1比1將兩個電感藉由水平對稱圍繞方式完成一變壓器設計，大量減少其晶片面積。為提供四相位輸入予單側邊混頻器使用，此論文中提出一新穎的四相位輸入四相位輸出除三電路。此電路利用真實單相時脈技術的邏輯電路實現除三以及脈波寬度50%輸出。此除三電路最大操作頻率為2.5 GHz，然而在此處應用中操作頻率為1,584 MHz。電路低功耗與低複雜度為此電路架構設計主要特點。
此鎖相迴路利用台積電0.18-m 1P6M CMOS製程完成其晶片設計。其電路鎖定之相位雜訊在頻率位移為1 MHz時的量測平均值為-106 dBc/Hz，輸出功率為-6 dBm，其訊號抖動為5.82 ps (p-p)。整體晶片面積為1.1 mm × 1.1 mm (包含bonding pads) 消耗功率為26 mW (不包含輸出緩衝級)。
附錄為頻帶選擇器(亦即，多工器)與單側邊頻帶混頻器之電路設計模擬與介紹。多工器部分包含二選一多工器與三選一多工器。其中二選一多工器分別選擇6,336 MHz與3,168 MHz；三選一多工器則分別選擇1,320 MHz、792 MHz與264 MHz。其兩組多工器總消耗功率約為7.5mW。單側邊混頻器則包含以電阻為負載與共振腔為負載兩種架構模擬。使用電阻做為負載之單側邊混頻器欲混出頻率2,640MHz，而利用共振腔為負載之單側邊混頻器欲混出的頻率為7,656 MHz、7,128 MHz、6,600 MHz、4,488 MHz、3,960 MHz與3,432 MHz六個頻率。此兩個單側邊混頻器總消耗功率約為15 mW。

The frequency synthesizer is very important circuit of wireless communication system. To achieve different communication system standards, the frequency plan and specifications are also dissimilar. In this thesis a Phase Locked Loop (PLL) is designed for the Multi-Band Orthogonal Frequency Division Multiplexing (MB-OFDM) Ultra Wide Band (UWB) application.
The PLL is operated at 6,336 MHz with 528 MHz reference input. The characteristics of this PLL are that it contains a Colpitts Voltage Control Oscillator (VCO) with transformer tank and a True Singe Phase Clock (TSPC) quadrature divide-by3 frequency divider. Besides, the power consumption of the PLL is low. To reduce chip area, the planar transformer is constructed by inter-wound metal conductors and consisted of two TSMC symmetric spiral inductors with turn ratio 1:1. A novel quadrature TSPC divide-by-3 circuit is proposed in this thesis. By using TSPC technology, the function of division-by-3 and 50% duty cycle quadrature outputs can be obtained for Single Side-Band (SSB) mixer use.
The divide-by-3 adopted TSPC technique could generate 50% duty cycle quadrature outputs for single side-band SSB mixer.
The maximum operation frequency of our designed quadrature TSPC divide-by-3 circuit is 2.5 GHz, while it is operated at 1,584 MHz in our application. The main advantages of this proposed divider are low circuit complex and low power consumption.
The PLL design was fabricated in a TSMC 0.18m 1P6M CMOS process. The measured average phase noise of the PLL is -106 dBc/Hz at 1 MHz offset from the center frequency. The output power is -6 dBm and the jitter is 5.82 ps (p-p). The total chip area is 1.1 mm × 1.1 mm and the power consumption is 26 mW, excluding that of output buffers.
The design work of band selectors (i.e., multiplexers) and Single Side-Band (SSB) mixers are demonstrated in the appendix. Two band selectors, one is a bi-way multiplexer for the frequency selection of 6,336 MHz or 3,168MHz and the other is a tri-way multiplexer for 1,320MHz, 792MHz, or 264MHz, are designed for the integration of MB-OFDM frequency synthesizer in the future. The total power consumption of these two selectors is 7.5 mW. Two SSB mixers are also designed for the integration of MB-OFDM frequency synthesizer, too. The types of SSB mixer output loads consist of resistive type and LC-resonant type. The output frequency of SSB mixer with resistive load is 2,640MHz and that of another SSB mixer with LC-tank load are 7,656 MHz, 7,128MHz, 6,600MHz, 4,488MHz, 3,960MHz and 3,432MHz。The total power consumption of these two SSB mixers is 15 mW。

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