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研究生： 陳亭諮
Chen, Ting-Zi
論文名稱： 一個混合電阻串與電容陣列架構的逐漸趨近式類比數位轉換器
A Successive Approximation ADC with Resistor-Capacitor Hybrid Structure
指導教授： 張順志
Chang, Soon-Jyh
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2012
畢業學年度： 100
語文別： 英文
論文頁數： 98
中文關鍵詞： 數位至類比轉換器 、逐漸趨近式類比數位轉換器
外文關鍵詞： ADC, SAR ADC
相關次數： 點閱：83  下載：11 
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    • 本論文使用一電阻串結合電容陣列，重新安排切換方式，實現了一個十位元每秒取樣五千萬次，具有低輸入電容特性的逐漸趨近式類比至數位轉換器。此類比至數位轉換器具備輔助預測電路，可避免DAC中不必要的電容切換；並且運用管線式類比至數位轉換器常用的每級解1.5位元的架構，減輕粗解類比至數位轉換器的比較器設計困難度。此外，此類比至數位轉換器採用電容電阻的混合數位至類比轉換器架構而不用純電容陣列，因此只需要六位元的數位轉類比電容陣列架構，即可達到十位元數位至類比轉換器的要求，因此可大量減少電容陣列的大小、節省晶片面積。除此之外，為了更進一步增進取樣頻率，此逐漸趨近式類比至數位轉換器採用了非同步控制省去一個高頻時脈產生器的需求。再者，使用了分散單調式電容切換的技巧，可以有效地控制比較器的動態偏移量。
    本設計使用台積電90-nm 1P9M CMOS製程來實作晶片，其核心電路面積為220μm × 190μm。在1.2伏特的電壓下，其總消耗功率為0.703毫瓦，有效位元9.3 bits，等效的FoM為28 fJ/conversion-step，而差動非線性與積分非線性峰值分別為-0.49/0.58 LSB與-0.95/1.1 LSB。

    This thesis presents a 10-bit 50MS/S successive approximation ADC with low input capacitance that uses an on-chip resistive ladder and capacitor array to arrange a new switching scheme. This analog to digital converter possesses a predictive circuit in order to avoid unnecessary switching in DAC network. In addition, the proposed SAR ADC manipulates the concept of 1.5-bit/stage, which is usually employed in pipelined ADC to ease the design of coarse ADC. Besides, the ADC adopts hybrid capacitive and resistance DAC rather than a pure capacitive one. With this hybrid DAC, the total capacitance of the DAC can be largely reduced. For the sake of enhancing sampling frequency, the ADC uses asynchronous timing control technique to remove the high frequency clock generator. Moreover, the splitting monotonic switching procedure is adopted to reduce the signal-dependent dynamic offset of comparator for maintaining good ADC linearity.
    This work is fabricated in TSMC 90-nm 1P9M CMOS process, and occupies 220μm × 190μm active area. This prototype chip consumes 0.703 mW from a 1.2-V supply and the effective number of bits (ENOB) is 9.3 bits. The resultant FOM is 28 fJ/conversion-step. The peak DNL and INL are -0.49/0.58 LSB and -0.95/1.1 LSB, respectively.

    摘要 I Abstract II 誌謝 IV List of Tables VIII List of Figures IX Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Organization 5 Chapter 2 Fundamentals of Analog-to-Digital Converter 6 2.1 Introduction 6 2.2 ADC Performance Metrics 7 2.2.1 Resolution and Accuracy 8 2.2.2 Static Specifications 9 2.2.2.1 Offset Error 9 2.2.2.2 Gain Error 10 2.2.2.3 Nonlinearity 11 2.2.3 Dynamic Specifications 14 2.2.3.1 Signal-to-Noise Ratio 14 2.2.3.2 Signal-to-Noise and Distortion Ratio 16 2.2.3.3 Effective Number of Bits 16 2.2.3.4 Dynamic Range (DR) 17 2.2.3.5 Effective Resolution Bandwidth (ERBW) 18 2.2.3.6 Spurious-Free Dynamic Range 19 2.2.3.7 Total Harmonic Distortion 20 2.2.3.8 Figure-of-Merit (FoM) 21 2.3 Review of ADC Architectures 21 2.3.1 Flash ADC 22 2.3.2 Pipelined ADC 23 2.3.3 Hybrid Architecture 25 2.3.3.1 Two-Step Architecture 25 2.3.3.2 Subrange ADC 26 Chapter 3 Successive Approximation Register Analog-to-Digital Converter 28 3.1 Introduction 28 3.2 The Architecture of SAR ADC 29 3.2.1 Charge-Redistribution SAR ADC 29 3.2.2 Charge-Sharing SAR ADC 33 3.3 Asynchronous Processing Technique 36 3.4 Capacitor Switching Procedure 39 3.4.1 Conventional Capacitor Switching Procedure 39 3.4.2 Split Capacitor Switching Procedure [26] [27] 41 3.4.3 Energy Saving Switching Procedure [28] 42 3.4.4 Merged Capacitor Switching Procedure [29][30] 43 3.4.5 Monotonic Capacitor Switching Procedure [11] 45 3.4.6 Analysis of Switching Energy 46 3.4.7 Summary of Capacitor Switching Procedures 51 3.5 Predictive Capacitor Switching Procedure 53 3.5.1 Splitting Monotonic Capacitor Switching Procedure 53 3.5.2 Predictive Capacitor Switching Procedure 55 Chapter 4 A 10-bit 50-MS/s Asynchronous SAR ADC with Low Input Capacitance 58 4.1 Motivation 58 4.2 The Proposed Low Input Capacitor SAR ADC 60 4.3 Architecture and Operation 62 4.3.1 Architecture of The Proposed SAR ADC 62 4.3.2 DAC Incomplete Settling Tolerance 64 4.3.3 Switch The Reference Voltage with Single Unit Capacitor 65 4.3.4 Operation of The Proposed SAR ADC 67 4.4 Circuit Implementation 68 4.4.1 S/H Circuit 68 4.4.2 Timing Controller 70 4.4.3 Dynamic Comparator 73 4.4.4 Capacitor Array 76 4.4.5 Resistive Ladder 78 4.5 Layout 80 4.6 Simulation Results 81 4.7 Measurement Setup and Measurement Results 86 4.8 Comparison and Discussion 91 Chapter 5 Conclusions and Future Works 92 Bibliography 94

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