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研究生： 裘愉豪
Chiu, Yu-Hao
論文名稱： 使用晶片上校正實現每級1.5位元之低功率逐次逼近類比數位轉換器
An Implementation of 1.5 Bits/Stage Low Power Successive Approximation Register Analog to Digital Converter by Using on Chip Calibration
指導教授： 王駿發
Wang, Jhing-Fa
共同指導教授: 鄭光偉
Cheng, Kuang-Wei
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2015
畢業學年度： 103
語文別： 英文
論文頁數： 89
中文關鍵詞： 類比數位轉換器 、每級1.5位元 、低功率 、語音系統 、晶片設計
外文關鍵詞： Analog-to-Digital Converter, 1.5 bits/stage, low-power, audio system, chip design
相關次數： 點閱：122  下載：10 
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    • 在語音系統中，類比數位轉換器(analog-to-digital, ADC)扮演著重要的角色。而逐漸逼近式類比數位轉換器(successive approximate register ADCs, SAR ADCs)是一種低成本、低功耗、中等速率類型的類比數位轉換器，在語音系統上較受歡迎。
    本篇論文提出利用晶片上校正，並利用時域數位轉換器(time-to-digital converter)來實現每級1.5位元的晶片設計方法，使其在隨機電壓輸入時，有25%的機率其電容陣列不會轉換。因此轉換功率能夠降低。在單調轉換(monotonic switching)的配合下，可以有效降低功率消耗。另外我們還搭配冗位(redundancy bit)使比較錯誤的容錯率上升，在加上非同步時脈(asynchronous clock)的技術，令我們的系統時脈降低為原來的十五倍，以達到一個較低功耗的類比數位轉換器。
    實現方面，我們利用國家晶片系統設計中心(Chip Implementation Center, CIC)與台灣積體電路公司(TSMC)所提供的90奈米製程完成本晶片實作下線。晶片面積為0.29*0.28 mm2，消耗功率為1.215μW，工作頻率為100kHz，ENOB為11.16 bit。

    Analog-to-digital converters (ADCs) play an important role in audio system. Successive approximate register ADC (SAR ADC) is a low cost, low power consumption, medium speed ADC which is widely used in audio system.
    This study proposed on chip calibration to implement 1.5 bits/stage chip design with time-to-digital converter (TDC). There will be a 25% chance that the capacitor array will not switch with random input signals. Therefore, the switching energy can be lower. By combining the monotonic switching, it will efficiently reduce the power consumption. Additionally, we add the asynchronous clock technique for lower our system clock 15 times.
    For implementation, we have been tape-out in TSMC’s 90nm process via Chip Implementation Center (CIC). The chip area is 0.28*0.29 mm2, the power dissipation is 1.215uW, the operation frequency is 100 kHz and ENOB is 11.16.

    中文摘要 I Abstract II 誌 謝 III Content IV Figure List VII Table List X Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Organization 4 Chapter 2 Fundamentals of Successive Approximation Register ADC 5 2.1 Introduction to ADC Specifications 5 2.1.1 Resolution and Accuracy 5 2.1.2 Offset Error 6 2.1.3 Gain Error 7 2.1.4 Nonlinearity 7 2.1.5 Signal-to-Noise Ratio 9 2.1.6 Signal-to-Noise and Distortion Ratio 11 2.1.7 Effective Number of Bits 11 2.1.8 Spurious-Free Dynamic Range 12 2.1.9 Figure-of-Merit (FoM) 12 2.2 Conventional SAR ADC 12 2.2.1 Introduction to Conventional SAR ADC 13 2.2.2 Basic S/H Circuit Concept and Parameter 13 2.2.3 Basic Concept of Comparator 17 2.2.4 Conventional Capacitor Switching Procedure 19 2.3 Other Architectures of SAR ADC 20 2.3.1 Split Capacitor Switching Procedure [17] [18] 21 2.3.2 Energy Saving Switching Procedure [19] 22 2.3.3 Merged Capacitor Switching Procedure [20] [21] 23 2.3.4 Monotonic Capacitor Switching Procedure [5] 24 2.4 Analysis of Switching Energy of All Method 26 2.5 Introduction to Synchronous and Asynchronous Clock 34 2.6 Redundancy Bits in SAR ADC 37 2.7 Choose of Unit Capacitance 38 Chapter 3 1.5 Bits/Stage Algorithm and Architecture in SAR ADC 40 3.1 Introduction to 1.5 Bits/Stage Algorithm in Pipeline ADC 40 3.1.1 1-Bit Per Stage in Pipeline ADC 40 3.1.2 1.5 Bits Per Stage in Pipeline ADC 42 3.1.3 1.5-Bit Per Stage in SAR ADC 44 3.2 The Optimize Stages Used for 1.5 Bits/Stage 46 3.2.1 Calculation of Optimize Stages Used for 1.5 Bits/Stage 46 3.2.2 Simulation of Optimize Stages Used for 1.5 Bits/Stage 49 3.2.3 Calculation of Optimize Stages Used for 1.5 Bits/Stage by Using Ramp Wave 51 3.3 Architecture of 1.5 Bits/Stage SAR ADC 52 3.3.1 Literature study of 1.5 Bits/Stage SAR ADC 53 3.3.2 A Novel Method for Implementation of 1.5 Bits/Stage Algorithm in Successive Approximate Register ADC 54 3.3.3 State Machine 55 3.3.4 Reference Input Generation 56 3.3.5 Delay Cell 56 3.3.6 Basic Concept of Time-to-Digital Converter 57 3.3.7 Overall Time-to-Digital Converter Architecture 58 3.4 Design Consideration 59 3.4.1 Resolution of Delay Cell 59 3.4.2 The Stage Use for Monotonic 61 3.4.3 Timing Violation Between TDC and Decoder. 62 3.5 Summary of Average Switching Energy 63 Chapter 4 Implementations and Simulation Results 67 4.1 Simulation Results 67 4.1.1 Implementation and Simulation of Bootstrapped Switch 67 4.1.2 Implementation and Simulation Result of Dynamic Comparator 69 4.1.3 Floor Plan and Simulation Results of Capacitor Array 72 4.1.4 Discuss of The Process Variation in TDC 74 4.1.5 Simulation of Differential Input of Comparator 74 4.1.6 Simulation of Time-to-Digital Converter 75 4.1.7 Simulation Result of ENOB 77 4.1.8 Simulation Result of Linearity 79 4.2 Comparisons and Discussions 83 4.3 Layout 83 4.4 Measurement Environment 83 Chapter 5 Conclusion and Future Work 85 5.1 Conclusion 85 5.2 Future Work 86 References 87

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