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研究生： 張少庭
Chang, Shao-Ting
論文名稱： 應用於超低功耗發射機之具誤差補償多相位產生器的分數型頻率合成器
A Fractional-N Frequency Synthesizer with Error Compensated Multi-Phase Generator for Ultra-Low Power Transmitter
指導教授： 鄭光偉
Cheng, Kuang-Wei
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2023
畢業學年度： 111
語文別： 英文
論文頁數： 76
中文關鍵詞： 超低功耗發射機 、頻率合成器 、相位旋轉器 、三角積分相位旋轉器 、多相濾波器 、雙端石英振盪器
外文關鍵詞： Ultra-low power transmitter, frequency synthesizer, phase rotator, delta-sigma phase rotator, polyphase filter, differential crystal oscillator
相關次數： 點閱：107  下載：17 
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    • 本論文提出了一種用於物聯網應用的無線傳感器網絡中超低功耗發射器的頻率合成器。與在載波頻率上進行調製的傳統發射機相比，我們團隊的發射機在較低頻率下實現了頻率合成。通過採用注入鎖定(Injection-Locked)和邊緣組合功率放大器(Edge-Combining Power Amplifiers )進行倍頻，超低功耗發射機可以在433MHz 頻段實現頻移鍵控 (FSK) 調製，同時保持低功耗和低雜訊性能。該合成器通過使用相位旋轉器（Phase rotator）結合三角積分調變器（DSM），實現輸出頻率範圍在41.88MHz至44.5MHz之間。相位旋轉器所需的輸入相位由雙端石英振盪器結合16相位多相濾波器（16-phase Polyphase Filter）產生，並透過使用誤差補償技術減輕多相濾波器的系統相位不平衡，從而實現低功率和低帶內相位噪聲。
    該設計採用90奈米互補式金屬氧化物半導體製程製造，工作電壓為0.8伏特，整體功率消耗為414微瓦。

    This thesis presents a frequency synthesizer for ultra-low-power transmitters in wireless sensor networks for IoT applications. Compared to conventional transmitters that perform modulation at the carrier frequency, our team's transmitter achieves frequency synthesis at a lower frequency. By incorporating injection-locked and edge-combining power amplifiers for frequency multiplying, the ultra-low-power transmitter can achieve frequency shift keying (FSK) modulation in the 433MHz ISM band while maintaining low power consumption and noise performance. The synthesizer combines a phase rotator with a delta-sigma modulator (DSM) to achieve an output frequency range of 41.88MHz to 44.5MHz. The required input phase for the phase rotator is generated by a differential crystal oscillator integrated with a 16-phase polyphase filter. The systematic phase imbalance of the polyphase filter is mitigated using error compensated techniques, resulting in low power and low in-band phase noise.
    The design is implemented in 90nm complementary metal-oxide-semiconductor (CMOS) process, operating at a voltage of 0.8V, with a total power consumption of 414μW.

    List of Figure VIII List of Tables XI Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Organization 2 Chapter 2 Literature Review 3 2.1 Frequency Synthesizer in Ultra Low Power Transmitters 4 2.1.1 PLL Based Frequency Synthesizer 4 2.1.2 Injection-Locked based Frequency Synthesizer 5 2.1.3 Phase Modulator based Frequency Synthesizer 7 2.2 Multi-Phase Generation in Frequency Synthesizer 9 2.2.1 DLL based Multi-Phase Generation 9 2.2.2 Phase Interpolator Based Multi-Phase Generation 9 2.2.3 Passive Component Multi-Phase Generation 10 2.3 Summary 14 Chapter 3 Low Power Transmitter and Fractional-N Frequency Synthesizer 15 3.1 Low Power Transmitter Architecture 15 3.2 Circuit Implements and Simulations 19 3.2.1 Differential Crystal Oscillator 20 3.2.2 16-Phase Polyphase Filter 30 3.2.3 Error Compensated Buffer 38 3.2.4 Phase Rotator 45 3.2.5 Second Order Delta-Sigma Modulator 48 3.3 Power Consumption 50 3.4 Corner Simulation 51 3.5 Noise Analysis 54 Chapter 4 Measurement Results 59 4.1 Test Setup and Measurement Results 59 4.1.1 Differential Crystal Oscillator 62 4.1.2 Frequency Synthesizer 64 4.1.3 Transmitter 68 4.2 Comparison Table 69 Chapter 5 Conclusion and Future Work 72 5.1 Conclusion 72 5.2 Future Work 73 Reference 74

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