在現今信號處理的應用上，隨著可攜式電子產品需求的快速成長，低功率、低成本的類比/數位轉換器於單晶片系統中為一重要的關鍵元件。本論文中，使用TSMC 0.18微米一層多晶矽六層金屬之互補式金氧半製程，提出一個由每級1.5位元組成具有十位元解析度且每秒取樣八千萬次的導管式類比/數位轉換器。為了降低此導管式類比/數位轉換器功率消耗，在設計中，運用了數個能節省功率的技術。省略前端取樣保持電路(Sample-and-Hold, S/H)。在倍乘式數位/類比轉換器中，使用了運算放大器共享技術(Opamp-Sharing Technique)。在針對導管式類比/數位轉換器的電容和運算放大器，運用比例縮小技術(Scaling Technique)。整個十位元的類比/數位轉換器只用了四級的運算放大器，再加上功率消耗在導管式類比/數位轉換器中比例縮小，所以減少整個類比/數位轉換器相當多的功率消耗。
在電路模擬方面，經由HSPICE補助設計軟體驗證結果，這個具十位元解析度每秒取樣八千萬次的導管式類比/數位轉換器，在輸入頻率三千萬赫茲下訊號對雜訊及失真比為57dB，在供應電壓1.8伏特下，整個電路的功率消耗為26mW，晶片的面積為1.33mm2。

For modern signal processing applications, low power, low cost analog-to-digital converter (ADC) is one of the key components in system-on-chip (SOC) with the expanding demand for portable products. In this thesis, a 10-bit 80-MHz pipelined ADC with 1.5-bit/stage architecture has been designed and implemented in the TSMC 0.18-μm 1P6M CMOS process. In order to reduce power consumption of the pipelined ADC, several low power techniques was adapted in circuit design. The front-end sample-and-hold circuit was removed. In multiplying digital-to-analog converter (MDAC), we use opamp-sharing technique and apply scaling technique for capacitor and opamp in pipelined ADC. Only four opamps are adapted, and power consumption of opamps was scaled down in pipelined ADC. So, large amount of pipelined ADC power consumption can be reduced.
The A/D converter is simulated and verified by HSPICE in circuit simulation. The signal-to-noise and distortion ratio (SNDR) of the pipelined ADC is 57dB with sampling frequency of 80MHz at input frequency 30MHz. Power consumption of this ADC is 26mW with 1.8V power supply, and chip area is 1.33mm2.

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