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研究生：	洪郁文 Hung, Yu-Wen
論文名稱：	H.264/AVC之管線化架構平行處理式解方塊濾波器 Pipeline Architecture for Parallel Processing Deblocking Filter in H.264/AVC
指導教授：	賴源泰 Lai, Yen-Tai
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2012
畢業學年度：	100
語文別：	英文
論文頁數：	69
中文關鍵詞：	H.264/AVC 、方塊效應、解方塊濾波器
外文關鍵詞：	H.264/AVC, Blocking Artifact, Deblocking Filter
相關次數：	點閱：118 下載：0
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由於網路的迅速發展，視訊多媒體在日常生活中已經扮演著人們不可或缺的重要角色。H.264/AVC是新一代的動態影像壓縮標準，與過去的其他標準相比，有著較高的壓縮效率，但這也使得他的運算複雜度比過去的標準要來的高。
　　在影像編碼時，因為高壓縮率所需較大的量化參數會造成區塊與區塊之間邊界變的不連續，而在H.264最明顯見到的現象為方塊效應，為了減少方塊效應的產生，H.264便在解碼迴圈當中採用了解方塊濾波器做為他的主要方塊，進而增加影像的品質。
　　本論文中，我們提出了平行處理式的解方塊濾波器以管線化的架構來處理，和傳統的解方塊濾波器相比，不但可以用較少的時脈處理完一個巨方塊，也可以有效地降低記憶體需求，增加處理效能，以達到改善的目的。

Due to the rapid spread of Internet, multimedia plays an important role in daily life. H.264/AVC is a newly video compression standard, compared with the past standards, it has high compression efficiency, but it has high computational complexity as well.
In the image compression process, because high compression rate requires larger quantization parameter, the boundary between the blocks becomes discontinuous. The most obvious phenomenon in the H.264 is the blocking artifact. In order to reduce the blocking artifact, H.264 adapted the deblocking filter as its main block in the decoder loop, it increases the image quality.
In this thesis, we proposed a parallel processing deblocking filter with pipeline architecture, compared to the traditional deblocking filter, it takes less clock cycles to process a maroblock, and moreover, it reduces the memory requirement effectively.

Table of Contents
Abstract
Table of Content
List of Tables
List of Figures


Chapter 1 Introduction ….………………………………….…….1

1.1 Motivation……………………………….……………………...2

1.2 Contributions……………………………………………………3

1.3 Thesis Organization.……………………………………….…... 3

Chapter 2 H.264/AVC ……………………… ……………………4

2.1 Introduction of H.264/AVC………………………..………........4

2.2 Inter Prediction………………………………………………….6

2.2.1 Tree Structured Motion Compensation……………………….7

2.2.2 Motion Vectors………………………………………………..8

2.2.3 Multiple Reference Frame…………………………………...10

2.3 Intra Prediction………………………………………………...11

2.3.1 Intra 4x4 Luma Prediction Modes…………………………...11

2.3.2 Intra 16x16 Luma Prediction Modes………………………...13
2.3.3 Intra 8x8 Chroma Prediction Modes………………………...14

2.4 Transform and Quantization…………………………………...15

2.5 Entropy Coding………………………………………………...16

Chapter 3 Background and Algorithn of Deblocking Filter…...18

3.1 Overview of Deblocking Filter………………………………..18

3.2 Deblocking Filter Algorithm…………………………………..20

3.2.1 Block Edge Level Adaptivity………………………………..22

3.2.2 Sample Level Adaptivity…………………………………….23

3.2.3 Slice Level Adaptivity……………………………………….26

3.3 Computation of Boundary Strength…..………………………..27

3.4 Filtering Operation…………………………………………….28

3.4.1 Clipping Operation…………………………………………..29

3.4.2 Standard Filtering……………………………………………30

3.4.3 Strong Filtering………………………………………………31

Chapter 4 Proposed Deblocking Filter Architecture…………...33

4.1 Previous Work………………………………………………….33

4.2 Analysis of Processing Order………………………………….34

4.3 Proposed Architecture………………………………………….40

4.4 Edge filter……………………………………………………...41

4.4.1 Horizontal Filtering Unit…………………………………….42

4.4.2 Vertical Filtering Unit….…………………………………….44

4.5 Memory Organization…………………………………...……..45

4.6 Shift Register………………………..…………………………47

4.7 Transpose Buffer……………………………………………….48

4.8 Control Unit……………………………………………………49

4.9 Overall Architecture…………………………………………...50

4.10 Operation Flow……………………………………………….52

Chapter 5 Experimental Results………………………………...59

5.1 Synthesis Results………………………………………………59

5.1.1 Timing Report………………………………………………..60

5.1.2 Area Report…………………………………………………..64

5.2 Comparisons…………………………………………………...65

Chapter 6 Conclusion……..……………………………………...66

References…………………………………………………………67


List of Tables
Table 3.1: Lookup table with the threshold values α and β………………………….26
Table 3.2: Lookup table with the clip value c1………………………………………30
Table 5.1: Comparisons with other work…………………………………………….65

List of Figures
Figure 1.1: Block diagram of H.264/AVC……………………………..……………...2
Figure 2.1: (a) H.264/AVC Encoder (b) H.264/AVC Decoder………………………..5
Figure 2.2: Macroblock and sub-macroblock partitions………………………………7
Figure 2.3: Example of integer and sub-sample prediction……………………………8
         (a) 4x4 block in current frame 
(b) Reference block: vector (1, -1) 
(c) Reference block: vector (0.75, -0.5)
Figure 2.4: Interpolation of half-pixel accuracy……………………………………….9
Figure 2.5: Interpolation of quarter-pixel accuracy……………………………………9
Figure 2.6: Multiple reference frames motion estimation……………………………10
Figure 2.7: Intra 4×4 luma prediction modes ………………………………………..12
(a) A 4×4 block with its neighboring pixels 
(b) Directions of eight 4×4 prediction modes and DC mode
Figure 2.8: 4 × 4 luma prediction modes…………………………………………….12
Figure 2.9: Intra 16 × 16 prediction modes…………………………………………..13
Figure 2.10: Intra 8×8 chroma prediction modes…………………………………….14
Figure 2.11: Scanning order of residual blocks within a macroblock…………….….15
Figure 3.1: (a) decoding without filtering (b) decoding with filtering……………….19
Figure 3.2: Macroblock representation of deblocking filter in H.264/AVC………….20
Figure 3.3: Processing order of the traditional deblocking filter in H.264/AVC…….21
Figure 3.4: Flowchart of the boundary strength determination………………………22
Figure 3.5: Threshold values principle of the deblocking filter……………………...24
Figure 3.6: Vertical, horizontal edge boundaries, and its sample in the macroblock...24
Figure 3.7: Flowchart of determining boundary strength….……………………..…..27
Figure 3.8: Flowchart of the standard filtering (BS=1, 2 or 3)………………………31
Figure 3.9: Flowchart of the strong filtering (BS=4)………………………………...32
Figure 4.1: Traditional processing order……………………………………………..35
Figure 4.2: 1-D processing order………………………………………..……………36
Figure 4.3: Hybrid processing order…………………………………………………37
Figure 4.4: 2-D processing order……………………………………………………..38
Figure 4.5: 2-D parallel processing order…………………………………………….39
Figure 4.6: Propose parallel processing order………………………………………..40
Figure 4.7: Propose edge filter architecture………………………………………….42
Figure 4.8: Operation across a vertical edge of the 4x4 block……………………….43
Figure 4.9: Operation across a horizontal edge of the 4x4 block…………………….45
Figure 4.10: Organization of SRAMs………………………………………………..46
Figure 4.11: LOP data structure of the proposed deblocking filter…………………..47
Figure 4.12: Shift register…………………………………………………………….47
Figure 4.13: Transpose buffer………………………………………………………..48
Figure 4.14: Transpose operation…………………………………………………….49
Figure 4.15: Overall deblocking filter architecture ………………………………….50
Figure 4.16: Propose parallel processing order………………………………………52
Figure 4.17: Data flow for step 0…………………………………………………….53
Figure 4.18: Data flow for step 1…………………………………………………….54
Figure 4.19: Data flow for step 2…………………………………………………….55
Figure 4.20: Data flow for step 3…………………………………………………….56
Figure 4.21: Data flow for step 9…………………………………………………….57
Figure 4.22: Processing Schedule……………………………………………………58
Figure 5.1: Synthesis Architecture…………………………………………………...59 

                                    

[1] “Draft ITU-T Recommendation and Final Draft International Standard of Joint Video Specification (ITU-T Rec. H.264|ISO/IEC 14496-10 AVC) ,” JVT-G050, 2003

[2] Gary J. Sullivan, Pankaj Topiwala, and Ajay Luthra, “The H.264/AVC Advanced Video Coding Standard: Overview and Introduction to the Fidelity Range Extensions,” Conference on Applications of Digital Image Processing, SPIE, 2004

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[4] Chao-Chung Cheng, Tian-Sheuan Chang, Member, IEEE, and Kun-Bin Lee, “An In-Place Architecture for The Deblocking Filter in H.264/AVC,” IEEE Transactions on Circuits and Systems, 2006 , Page(s): 530 - 534

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[9] Thomas Wiegand, Gary J. Sullivan, Gisle Bjontegaard, and Ajay Luthra, “Overview of the H.264 / AVC Video Coding Standard,” IEEE Transactions on Circuits And Systems For Video Technology, 2003.

[10] Ralf Schafer, Thomas Wiegand and Heiko Schwarz, “The emerging H.264/AVC standard,” EBU Technical Review, 2003

[11] Y. W. Huang, T. W. Chen, B. Y. Hsieh, T. C. Wang, T. H. Chang, and L. G. Chen, “Architecture Design for Deblocking Filter in H.264/JVT/AVC,” IEEE International Conference on Multimedia and Expo, 2003, Page(s): I - 693-6 vol.1

[12] B. Sheng, W. Gao, and D. Wu, “An Implemented Architecture of Deblocking Filter for H.264/AVC,” IEEE International Conference on Image Processing, 2004, Page(s): 665 - 668 Vol. 1

[13] M. Parlak and I. Hamzaoglu, “Low Power H.264 Deblocking Filter Hardware Implementations,” IEEE Transactions on Consumer Electronics, 2008, Page(s): 808 - 816

[14] G. Khurana, A. A. Kassim, T. P. Chua, Bi Mi M., “A Pipelined Hardware Implementation of In-loop Deblocking Filter in H.264/AVC,” IEEE Transactions on Consumer Electronics, 2006, Page(s): 536 - 540

[15] K. Xu and C. S. Choy, “A Five-Stage Pipeline, 204 Cycles/MB, Single-Port SRAM-Based Deblocking Filter for H.264/AVC”, IEEE Transactions on Circuits and Systems for Video Technology, 2008, Page(s): 363 - 374

[16] C. C. Cheng, T. S. Chang, K. B. Lee, “An In-Place Architecture for the Deblocking Filter in H.264/AVC”, IEEE Transactions on Circuits and Systems for Video Technology, 2006, Page(s): 530 - 534

[17] C. C. Cheng, T. S. Chang, “An Hardware Efficient Deblocking Filter for H.264/AVC”, IEEE Consumer Electronics, 2005, Page(s): 235 - 236

[18] T. M. Liu, W. P. Lee, C. Y. Lee, “An In/Post-Loop Deblocking Filter With Hybrid Filtering Schedule”, IEEE Transactions on Circuits and Systems for Video Technology, 2007, Page(s): 937 - 943

[19] C. M. Chen and C. H. Chen, “An Efficient Architecture for Deblocking Filter in H.264/AVC Video Coding,” IASTED International Conference on Computer Graphics and Imaging, 2008

[20] The H.264/AVC Reference Software (JM18.0), http://iphome.hhi.de/suehring/tml/download/

校內：2022-01-01公開
校外：不公開電子論文尚未授權公開，紙本請查館藏目錄

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