針對循環式類比/數位轉換器(ADC)，本論文提出兩種電容切換技術，名為隨機回授電容互換(random feedback-capacitor interchanging, RFCI)及平均隨機回授電容互換(averaging random feedback-capacitor interchanging, ARFCI)，用來降低因為電容不匹配所造成的諧波失真。RFCI技術可以在不犧牲Nyquist頻率訊號對雜訊暨失真比的情況下，改善傳統ADC的無諧波失真動態範圍，而ARFCI擁有比RFCI好的SNDR特性，但ARFCI的SFDR改善能力沒有RFCI來得好。現存之回授電容交換(commutated feedback-capacitor switching, CFCS)技術雖然不太能改善循環式ADC的SFDR但確能改善其SNR。因此，本論文提出一個可重新設定的循環式ADC架構，此架構可以透過簡單的時序控制電路來輕易地設定成RFCI、ARFCI及CFCS其中一種技術。此一可重新設定的架構，以一個智財(intellectual property, IP)提供了三種轉換特性而不是三個分離的智財，因此大為提升了循環式ADC的能力。一種前端循環電容誤差平均技術亦被提出來改善循環式類比/數位轉換器在解析度與速度的取捨之靈活度。此技術只需簡單的結構而能改善figure of merit (FOM)。一個使用0.35um 2P4M 3.3V CMOS製程設計的單晶片被實現與量測以驗證所提技術之效果。此晶片大小尺寸為0.63 mm2。量測結果顯示RFCI對此轉換器相較於傳統技術分別提升7 dB與0.5 dB的SFDR與SNDR。而ARFCI相較於傳統技術則分別提升10 dB與6 dB的SFDR與SNDR，而轉換速率則降為12/13倍。所使用的前端循環電容誤差平均技術則使FOM大幅降低為使用傳統技術時的0.55倍。
本論文亦提出一偏壓及輸入互換(BII)技術以重設運算放大器(opamp)的總和節點(summing node)，藉此消除使用共享運算放大器(opamp sharing)之架構的循環式與導管式ADC的殘值記憶效應。不同於其他運算放大器總和節點重設(OSNR)技術，所提出之BII技術不需要額外的前級放大器(preamplifier)也不需犧牲信號振幅(signal swing)。因此驅動電路的大小與功率消耗皆可減少。在此技術中，全差動(fully differential)與偽差動(pseudo-differential) BII放大器架構被發展出來。簡單的浮動互連(floating interconnection)技術亦被提出來解決在偽差動架構中共模偏差(common-mode offset)放大的問題。與其他OSNR技術相比，使用0.18um 1.8V CMOS製程設計10位元每秒8千萬次取樣之概念驗證用轉換器證實了所提出之BII技術能更有效地以較少的功率消耗及較大的信號振幅達成重設運算放大器總和節點之目的。其中FD-BII ADC 顯示57.2 dB的SNDR與64.7 dB 的SFDR並消耗20 mW的類比電路功率。而PD-BII ADC 顯示58.7 dB的SNDR與68.3 dB 的SFDR並消耗14 mW的類比電路功率。
最後，本論文提出一個平均式相關雙重取樣技術(averaging correlated double sampling, ACDS)以同時減少循環式/導管式(cyclic/pipelined)類比/數位轉換器中的電容不匹配誤差與有限運算放大器增益誤差。平均式相關雙重取樣技術在兩個放大相位之間產生互補的誤差並加以平均。此平均式相關雙重取樣技術能夠與運算放大器共享架構相結合而不會再增加更多的時脈相位。由於對電容不匹配與有限運算放大器增益的敏感度降低，電容性負載與運算放大器能夠以較小的尺寸被設計，也因此可以降低類比/數位轉換器的成本與功率消耗。除此之外，平均式相關雙重取樣技術與運算放大器共享技術的結合亦可再進一步節省類比/數位轉換器的成本與功率消耗。所提出之平均式相關雙重取樣技術不需要複雜的結構或額外的校正電路，因而此技術適合被循環式/導管式類比/數位轉換器用來達成高解析、低成本及低功耗之特性。在運算放大器增益為1000及電容不匹配為0.4%的條件下，模擬結果顯示使用平均式相關雙重取樣技術之轉換器比起傳統轉換器可分別提升33.5 dB與27.7 dB的SFDR與SNDR。

This dissertation proposes two capacitor-swapping techniques, random feedback-capacitor interchanging (RFCI) and averaging RFCI (ARFCI) techniques, for cyclic analog-to-digital converters (ADCs) to reduce the harmonic distortion caused by capacitor mismatch. The RFCI technique improves upon the SFDR of conventional ADCs without sacrificing the SNDR. The ARFCI technique has better SNDR characteristics but less SFDR improvement than RFCI. The prior commutated feedback-capacitor switching (CFCS) technique can improve the SNR of ADCs. Therefore, this work proposes a reconfigurable cyclic ADC architecture that can be easily reconfigured to operate with one of the RFCI, ARFCI, and CFCS techniques by a simple timing control circuit. This reconfigurable topology provides three conversion characteristics with one item of intellectual property (IP) and thus greatly enhances the capabilities of cyclic ADCs. A leading-subcycles capacitor-error averaging (LCEA) scheme is also proposed to improve the flexibility of cyclic ADCs in the accuracy-speed tradeoff with simple structures. It can be used to enhance the figure of merit (FOM) of cyclic ADCs. A chip with 0.35um 2P4M 3.3V CMOS process is implemented and measured to demonstrate the proposed approaches. The chip size is 0.63 mm2. Measurement results show that the RFCI technique has about 7 dB and 0.5 dB higher SFDR and SNDR, respectively, than the conventional technique for the ADC. The ARFCI technique has about 10 dB and 6 dB higher SFDR and SNDR, respectively, than the conventional technique, while the conversion rate becomes 12/13 of that of the conventional technique. With the LCEA scheme, the measured FOM is greatly reduced to 0.55 times of that obtained using the conventional technique.
This dissertation also proposes a bias-and-input interchanging (BII) technique that uses opamp summing node resetting (OSNR) to remove the memory effect of residue signals in cyclic/pipelined ADCs with opamp-sharing architectures. The proposed BII technique does not need an additional preamplifier stage or need to sacrifice signal swing, as do other OSNR techniques. Thus, the size of driving circuits and power consumption can be reduced. In the BII technique, fully differential (FD) and pseudo-differential (PD) BII opamp architectures are developed. Simple floating interconnection schemes are also proposed to eliminate the common-mode (CM) offset amplification for the PD architecture. 10-bit 80-MHz proof-of-concept ADCs with 0.18um 1.8V CMOS process confirm that the proposed BII technique can achieve OSNR more efficiently, using less power and achieving a wider signal swing than other OSNR techniques The FD-BII ADC shows a SNDR of 57.2 dB and a SFDR of 64.7 dB with an analog power of 20 mW. The PD-BII ADC shows a SNDR of 58.7 dB and a SFDR of 68.3 dB with an analog power of 14 mW.
Finally, this dissertation proposes an averaging correlated double sampling (ACDS) technique to reduce the capacitor mismatch error and finite opamp gain error of cyclic/pipelined ADCs simultaneously. The ACDS technique produces complementary errors between two amplifying phases, so that the errors can be averaged. The ACDS technique can be combined with the opamp sharing architecture without adding more clock phases. With reduced sensitivities to capacitor mismatch and finite opamp gain, smaller sizes of capacitive loads and opamps can be designed, which lowers the cost and power consumption of ADCs. The combination of the ACDS and opamp sharing techniques can further save more cost and power. With the assigned opamp gain of 1000 and 0.4% capacitor mismatch, simulations results show that the ADC with the ACDS has 33.5 dB and 27.7 dB higher SFDR and SNDR, respectively, than the conventional ADC.

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