隨著科技與製程技術不斷的進步，電腦與通訊等產品功能的急速提昇及多元化、可攜性與輕巧化的需求及面對產品上市時程（time-to-market）與生命週期短，系統晶片面臨了許多架構設計與開發上的挑戰。由上述趨勢可知，對於開發人員來說開發週期被大幅的縮減，為有效解決此問題並加速開發流程，提出了電子系統層級設計技術(Electronic System Level, ESL)作為設計與驗證的方法。傳統的晶片系統開發流程，軟體部分的開發必須等待硬體設計完成才能進行整合，此設計流程除了會造成開發上時程被拉長外，整合上也會因為軟硬體分別開發而產生不少問題。ESL方案的設計概念是在硬體開發初期，提供能讓軟體開發者進行軟硬體模擬的平台，以加快晶片設計的開發流程。本實驗室採用ESL方案自行設計通用型繪圖處理器，目標為適用於終端之高效能及低功耗加速處理器。
為加速開發流程，完善開發者在開發過程中使用的開發工具也是至關重要的，本論文針對本實驗室全系統模擬虛擬平台設計除錯系統。其設計可分為兩塊子系統，一個是軟體除錯工具設計，另一個是硬體模組支援除錯。
在本論文的ESL系統中，以QEMU虛擬機模擬開源指令架構RISC-V CPU，在虛擬機中移植客制化的除錯器，使其可針對運行在本實驗室以SystemC高階硬體描述語言開發的通用型繪圖處理器CASLab GPU上的平行程式進行除錯。於全模擬平台上支援除錯系統，能使目前仍在開發階段的CASLab GPU更有效率地進行除錯及後續開發。

With the dramatic increase in the complexity of electronic ICs, rapidly evolving technologies, and ever-changing markets, development times are becoming shorter and shorter. This paper describes the implementation of the debug system on the CASLab GPU-SIM full system simulation platform. The debug system and automatic development tools were introduced to ease the time-consuming work of developers and increase productivity in the CASLab-GPU development of hardware and software co-design environment.
To build the co-debugging system between the host CPU and the target GPU in our platform, the customized debugger and various debugging functions are integrated into the debugging environment. The design can be divided into two subsystems; one is the software debugging tool and the other is the hardware module that supports debugging. Supporting the debugging system on the full system simulation platform enables more efficient development of the CASLab GPU.

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