| 研究生: |
龔家和 Kung, Chia-Ho |
|---|---|
| 論文名稱: |
具有放大器共享與雜訊耦合技術的高通三角積分調變器 High-Pass Sigma–Delta Modulator with Operational Amplifier Sharing and Noise-Coupling Techniques |
| 指導教授: |
李順裕
Lee, Shuenn-Yuh |
| 學位類別: |
碩士 Master |
| 系所名稱: |
電機資訊學院 - 電機工程學系 Department of Electrical Engineering |
| 論文出版年: | 2022 |
| 畢業學年度: | 110 |
| 語文別: | 中文 |
| 論文頁數: | 70 |
| 中文關鍵詞: | 放大器共享技術 、雜訊耦合技術 、新型高通積分器 |
| 外文關鍵詞: | high-pass sigma–delta modulator, noise-coupling technique, operational amplifier sharing, high-pass integrator |
| 相關次數: | 點閱:89 下載:6 |
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本論文提出了一個應用在生理訊號擷取系統中的高通三角積分調變器電路,此電路使用了放大器共享與雜訊耦合的技術來達到低功率消耗與高精確度的表現。藉由放大器共享技術能使兩級積分器在時脈錯開的情況下結合,並共用一個放大器,故能大幅降低功率消耗,且能保持原有雜訊整形的階數。雜訊耦合技術則是能在不使用額外積分器的情況下,透過在原本就有的加法器上運作,可讓整體的雜訊整形階數再提升一階,使電路能有更高的精確度表現。除此之外,由於傳統高通積分器架構的電路實現方法會讓電容不匹配對電路表現有嚴重的影響,使電路更加敏感於製程變異,因此本篇論文提出了新型的高通積分器架構,除了能克服上述的問題,同時也能帶來其他好處,像是能讓高通積分器內部具有更低功率消耗的放大器,使量測結果展現不錯的技術指標。
晶片的實現使用了TSMC 0.18μm 1P6M的製程,而從量測的結果可以得知,在精確度的表現上,SNDR為75.26 dB,功率消耗的部分為1.524μW,證明此電路因為使用了上述的技術與提出新架構確實達到高精確度與低功率消耗的表現,使此電路在近幾年低速的三角積分調變器中具有非常大的優勢。
關鍵字:放大器共享技術、雜訊耦合技術、新型高通積分器
A 3rd-order feedforward High-Pass Sigma-Delta Modulator (HPSDM) with operational amplifier (op-amp) sharing and noise-coupling techniques is presented in this paper. The modulator is suitable for biomedical signal acquisition with features of high resolution and low power consumption. Op-amp sharing technique has been utilized to reduce the number of amplifiers. To add an additional noise-shaping order, the noise-coupling technique is embedded in the summing stage without additional amplifier. To overcome the circuit sensitivity to process variation and capacitor mismatch, a new high-pass integrator structure is proposed. Simulation results reveal a Signal-to-Noise and Distortion Ratio (SNDR) of 79.64 dB consuming 1.31 μW under 1.2 V supply, which can achieve peak Schreier Figure-of-Merit (FoM) of 161.64 dB and peak Walden FoM of 0.4 pJ/conv.
Keywords: high-pass sigma–delta modulator, noise-coupling technique, operational amplifier sharing, high-pass integrator
[1] National development council. “Elderly population schedule.”
https://www.ndc.gov.tw/Content_List.aspx?n=695E69E28C6AC7F3
[2] A. D. Krahn et al., “Use of an extended monitoring strategy in patients with problematic syncope,” Circulation, vol. 99, no. 3, pp. 406–410, Jan. 1999.
[3] Analog Device, AD8232, Single-Lead, Heart Rate Monitor Front End.
[4] J. Xu, S. Mitra, A. Matsumoto, S. Patki, C. V. Hoof, K. A. A. Makinwa, and R.F.Yazicioglu, “A Wearable 8-Channel Active-Electrode EEG/ETI Acquisition System for Body Area Networks,” IEEE J. Solid-State Circuits, vol. 49, no. 9, pp. 2005–2016, Sep. 2014.
[5] C. C. Enz and G. C. Temes, "Circuit techniques for reducing the effects of op-amp imperfections: Autozeroing, correlated double sampling, and chopper stabilization," Proc. IEEE, vol. 84, no. 11, pp. 1854-1614, Nov. 1996.
[6] P. Malcovati, S. Brigati, F. Franncesconi, F. Maloberti, and A. Baschirotto, “Behavioral modeling of switched-capacitor sigma-delta modulators,” IEEE Trans. Circuits Syst. 1, Fundam. Theory Appl., vol.50, no. 3, pp. 352-364, Mar. 2003.
[7] P. H. Su, K. L. Huang, and S. Y. Lee, “Operational amplifier sharing based high-pass sigma-delta modulator with programmable feedforward coefficients for ECG signal acquisition,” Proc. IEEE Int. Symp. Circuits Syst., Sevilla, pp. 1–4, Oct. 2020.
[8] S. Y. Lee, P. H. Su, K. L. Huang, Y. W. Hung and J. Y. Chen, "High-Pass Sigma–Delta Modulator With Techniques of Operational Amplifier Sharing and Programmable Feedforward Coefficients for ECG Signal Acquisition," IEEE Trans. Biomed. Circuits Syst., vol. 15, no. 3, pp. 443-453, June 2021.
[9] K. Chandrashekar, B. Bakkaloglu, “A 10 b 50MS/s opamp-sharing pipeline A/D with current-reuse OTAs,” IEEE Trans. Very Large Scale Integration (VLSI) Syst., vol. 19, no. 9, pp. 1610-1616, Sep. 2011.
[10] D. Kanemoto, T. Ido, K. Taniguchi, “A novel third order delta sigma modulator with one opamp shared among three integrator stages”, IEICE Electron. Express, vol. 5, no. 24, pp. 1088-1092, 2008.
[11] K. Lee, J. Chae, M. Aniya, K. Hamashita, K. Takasuka, S. Takeuchi, and G. C. Temes, “A noise-coupled time-interleaved ΔΣ ADC with 4.2 MHz Bandwidth, -98 dB THD and 79 dB SNDR,” IEEE J. Solid-State Circuits, Vol. 43, No. 12, pp. 2601–2612, Dec. 2008.
[12] Y. Wang, G. C. Temes, “Noise-Coupled Continuous-Time ΣΔ ADCs,” IET Electronics Letters 12th, Vol. 45, No. 6, March 2009.
[13] Zanbaghi, R.; Fiez, T.S.; Temes, G.; “A new zero-optimization scheme for noise-coupled ΣΔ ADCs,” in Pro. IEEE ISCAS 2010, pp.2163-2166, May 2010.
[14] Lin He; Yuncheng Zhang; Fang Long; Fengcheng Mei; Mingyuan Yu; Fujiang Lin; Libin Yao; Xicheng Jiang, "Digital Noise-Coupling Technique for Delta–Sigma Modulators With Segmented Quantization," Circuits and Systems II: Express Briefs, IEEE Transactions on , vol.61, no.6, pp.403,407, June 2014
[15] K. Kundert, “Simulating switched-capacitors filter with SpectreRF,” The Designer’s Guide Community, Jul. 2006 [Online]. Available: http://www.designers-guide.org/Analysis/sc-filters.pdf.
[16] S. Song et al., “A 430 nW 64 nV/√H z current-reuse telescopic amplifier for neural recording applications,” in Proc. IEEE Biomed. Circuits Syst. Conf. (BioCAS), Oct./Nov. 2013, pp. 322–325.
[17] A. Noman, M. Dessouky, and K. Sharaf, “A dual phase SC CMFB circuit for double sampling modulators,” IEEE 2003 46th Midwest Symposium on Circuits and Systems, pp. 287-290, Dec. 2003.
[18] B. Wicht, T. Nirschl, D. Schmitt-Landsiedel, “Yield and speed optimization of a latch-type voltage sense amplifier,” IEEE J. Solid-State Circuits, vol. 39, no. 7, pp. 1148-1158, July, 2004.
[19] Linear Technology. LT1763 Series 500mA, Low Noise, LDO Micropower Regulators in SO-8. [Online]. Available
https://www.analog.com/media/en/technical-documentation/data-sheets/1763fh.pdf
[20] Texas Instruments. TLV758P 500-mA, high-accuracy, adjustable LDO in SOT-23. [Online]. Available
https://www.ti.com/lit/ds/symlink/tlv758p.pdf
[21] Analog Deviced. AD8603 Precision Micropower, Low Noise CMOS, Rail-to-Rail Input/Output Operational Amplifiers in TSOT-23. [Online]. Available
https://www.analog.com/media/en/technical-documentation/data-sheets/AD8603_8607_8609.pdf
[22] S. Rout and W. Serdijn, "High-pass ∆∑ converter design using a state-space approach and its application to cardiac signal acquisition. " IEEE Trans. Biomed. Circuits Syst., vol. 12, no. 3, pp.483-494, Jun. 2018.
[23] J. Bang, H. Jeon, M. Je and G. Cho, "6.5μW 92.3dB-DR biopotentialrecording front-end with 360mVpp linear input range," 2018 IEEE Symposium on VLSI Circuits, Honolulu, 2018, pp. 239-240.
[24] H. Jeon, J. S. Bang, Y. Jung, I. Choi, and M. Je, “A high DR, DC coupled, time-based neural-recording IC with degeneration R-DAC for bidirectional neural interface,” IEEE J. Solid-State Circuits, vol. 54, no. 10, pp. 2658–2670, Oct. 2019.
[25] I.-J. Chao, B.-D. Liu, S.-J. Chang, C.-Y. Huang, and H.-W. Ting, “Analyses of splittable amplifier technique and cancellation of memory effect for opamp sharing,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 25, no. 2, pp. 621–634, Feb. 2017.
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