| 研究生: |
吳育樺 Wu, Yu-Hua |
|---|---|
| 論文名稱: |
以計數器為基礎且具不確定值閃避能力之輸出選擇方法 The Counter-Based Output Selection Method with Unknown-Preventing Capability |
| 指導教授: |
李昆忠
Lee, Kuen-Jong |
| 學位類別: |
碩士 Master |
| 系所名稱: |
電機資訊學院 - 電機工程學系 Department of Electrical Engineering |
| 論文出版年: | 2008 |
| 畢業學年度: | 96 |
| 語文別: | 英文 |
| 論文頁數: | 69 |
| 中文關鍵詞: | 壓縮 、測試 、輸出選擇 |
| 外文關鍵詞: | output selection, compaction, testing |
| 相關次數: | 點閱:104 下載:1 |
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在本篇論文中,我們提出了一個以計數器為基礎的輸出選擇方法,來解決超大型積體電路日益複雜龐大所造成的測試響應資料量過大及傳統壓縮器難以解決的失真、不確定值、不易診斷等相關問題。輸出選擇方法的基本概念是將錯誤響應資料藉由輸出選擇機制直接觀察,而不經過壓縮的動作,所以不會有前述的失真以及不確定值的問題發生。我們所提出的輸出選擇架構,主要的硬體組成為一個簡單的計數器及一多工器,所以需要的面積負擔非常的低且控制機制也非常簡單。針對所提出的架構,我們發展了一個不需修改自動測試向量產生器的動態選擇演算法,幫助我們藉由控制計數器的運作來有效的選擇所需觀察的輸出響應,達到資料壓縮的目的。實驗結果顯示,對大電路而言,即使使用非常緊密壓縮的測試向量,平均也能達到超過10倍的壓縮比率,更重要的是幾乎可以維持原有之錯誤診斷能力。此外我們也將不確定的影響考量進動態選擇演算法當中,來幫助我們除了選擇最少量的輸出響應之外,也盡量避免觀察到不確定的響應,進而提昇整體測試品質。針對ISCAS89及ITC99之標準電路所做的實驗結果顯示,在有2%不確定響應的分佈時,所有電路的錯誤皆能在不觀察到任何一個不確定的情況下被偵測到。即使不確定響應的分佈高達5%甚至10%,我們提出之輸出選擇觀察機制也能避開大部分電路之所有不確定響應。
In this thesis, we propose a novel output response compaction technique, called the Counter-Based Output Selection Method, to address the problems of large test volume, aliasing, unknown value (X) and difficult-to-diagnosis that commonly exist in traditional space/time compactors. The basic idea is to directly select only a subset of output bits for observation so as to achieve aliasing-free and X-tolerant capabilities. An ATPG- independent selection algorithm called the Dynamic Selection Procedure is developed to efficiently and effectively select the necessary output bits to observe based on the control of a simple counter. Experimental results show that on the average over 10x compaction ratio can be achieved even with highly compressed test sets. More importantly, we find that almost the same diagnosability achievable using the original test sets can be preserved. To make this technique more practical, the influence of unknown value is also considered. An output selection algorithm that can efficiently avoid the selection of unknown bits is developed. Experimental results show that for all ISCAS89 and ITC99 benchmark circuits, when 2% unknown bits are randomly inserted to the output response, the algorithm always can identify a control sequence for the counter to select a set of deterministic output bits to detect all detectable faults. Even for the cases where 5% or even higher (10%) unknowns present in the circuits, the developed algorithm can still avoid almost all unknown values by using a scan chain reordering procedure.
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