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研究生：	鄭晉偉 Cheng, Chin-Wei
論文名稱：	針對兩個具有偏移與增益不匹配的逐漸逼近式類比數位轉換器之無須校準設計技術 Calibration-Free Design Techniques for Two SAR ADCs with Offset and Gain Mismatches
指導教授：	張順志 Chang, Soon-Jyh
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2026
畢業學年度：	114
語文別：	英文
論文頁數：	125
中文關鍵詞：	逐漸趨近式類比數位轉換器、無須校正、偏移消除、增益誤差消除
外文關鍵詞：	successive approximation register (SAR) analog-to-digital converter (ADC), calibration-free, offset cancellation, gain mismatch cancellation
相關次數：	點閱：39 下載：0
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本論文提出一個應用於電容式觸控感測的十位元每秒取樣五千六百萬次雙通道逐漸逼近式類比數位轉換器陣列。為了在不增加背景校正演算法硬體負擔的情況下，滿足多點觸控的精準度與快速響應需求，本研究提出了一種無須校準的設計。本設計採用了次區間逐漸逼近式類比數位轉換器架構，並透過檢測跳過機制，以減少不必要的切換能量並減輕數位類比轉換器電容不匹配的影響。此外，本設計採用了殘值超取樣技術結合比較器輸入交換技術來進一步提升類比數位轉換器之線性度並實現偏移誤差消除。再者，本設計實現了此論文所提出的參考電壓緩衝器交換機制，消除通道間的增益不匹配。
本晶片使用台積電90奈米 CMOS 製程進行設計與下線驗證，核心電路面積為 0.382 mm²。在五千六百萬次的取樣率及1.1伏特的電源電壓下，雙通道陣列的總功耗為 4.34 毫瓦。量測結果顯示，當輸入訊號為一百萬赫茲時，峰值訊號雜訊與失真比為 56.70 dB；在兩千萬赫茲接近奈奎斯特頻率的輸入下，峰值訊號雜訊與失真比為 52.46 dB。在雙通道匹配效能上，通道間的靜態偏移差異僅 0.26最低有效位元。值得注意的是，在啟用參考電壓交換機制後，通道間增益誤差不匹配成功從3.51最低有效位元降低至1.33最低有效位元。在奈奎斯特頻率下，本設計的轉換效率為113.13 fJ/conversion-step。

This thesis presents a 10-bit 56-MS/s dual-channel successive approximation register (SAR) ADC array tailored for capacitive touch sensing applications. To meet the stringent demands for multi-touch accuracy and rapid response times without the hardware overhead of complex background calibration algorithms, a calibration-free design is presented. This design adopts a subranging SAR structure with a Detect-and-Skip (DAS) logic to reduce unnecessary switching energy and mitigate the impact of DAC mismatch. To further enhance linearity of ADC and implement offset cancellation, this ADC employs the second-order Residue Oversampling (ROSR2) combined with a comparator input-swapping technique. Furthermore, a reference voltage buffer swapping mechanism is proposed and implemented to intrinsically eliminate the inter-channel gain mismatch.
The proof-of-concept prototype was designed and fabricated in a TSMC 90-nm CMOS process. The active core area occupies 0.382 mm². Operating at a 56-MS/s sampling rate, the total power consumption of the dual-channel array is 4.34 mW from 1.1V supplies. The measurement results demonstrate that the ADC achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 56.70 dB at a 1-MHz input, and an SNDR of 52.46 dB at a near-Nyquist 20-MHz input. The inter-channel static offset difference is merely 0.26 LSB. Notably, with the reference swapping mechanism enabled, the average channel-to-channel gain error mismatch is successfully reduced from 3.51 LSB to 1.33 LSB. The achieved Walden Figure of Merit (FoM) is 113.13 fJ/conversion-step at the Nyquist frequency.

摘　要 I
Abstract II
Chapter 1 Introduction 1
1 Background and Motivation 1
2 Thesis Organization 3
Chapter 2 Fundamentals of Analog-to-Digital Converters 4
1 Basic Concepts of ADCs 4
1.1 Sampling Theorem and Anti-Aliasing 4
1.2 Quantization Error 6
2 ADC Specification 8
2.1 Static Specifications 8
2.1.1 Offset Error 8
2.1.2 Gain Error 9
2.1.3 Nonlinearity Error 10
2.2 Dynamic Specifications 13
2.2.1 Signal-to-Noise Ratio (SNR) 13
2.2.2 Total Harmonic Distortion (THD) 14
2.2.3 Signal-to-Noise and Distortion Ratio (SNDR) 15
2.2.4 Effective Number of Bits (ENOB) 16
2.2.5 Spurious-Free Dynamic Range (SFDR) 16
2.2.6 Effective Resolution Bandwidth (ERBW) 17
3 SAR ADC Architecture and Operation 18
3.1 Overview of SAR ADC Architecture 18
3.2 Sample-and-Hold (S/H) 19
3.3 Comparator 21
3.3.1 Comparator Speed 22
3.3.2 Comparator Noise 24
3.3.3 Comparator Offset 25
3.4 CDAC 26
3.4.1 Fundamental Architecture 26
3.4.2 Thermal Noise 26
3.4.3 Parasitic Capacitance and Gain Error 27
3.5 Reference Voltage Buffer 27
3.5.1 Challenge of Reference Voltage Stability 27
3.5.2 Analysis of Reference Voltage Variation 28
3.5.3 Analysis of Reference Settling 29
Chapter 3 Efficiency and Accuracy Enhancement Techniques in SAR ADCs 31
1 Redundancy Algorithm 31
1.1 Non-binary Approximation Algorithm 32
1.2 Binary-Scaled Error Compensation 33
2 Subranging SAR ADC 35
2.1 Detect-and-Skip (DAS) Algorithm 36
2.2 Aligned Switching Technique 38
3 Capacitor Switching Method 39
3.1 Monotonic Switching Method [11] 39
3.2 Split Switching Method [12] 41
3.3 Merge Capacitor Switching Method [13] 43
3.4 Switchback Switching Method [15] 44
4 Residue Oversampling (ROSR) Technique 46
4.1 Operation Principle of ROSR 46
4.2 Capacitor Shuffling Mechanism 47
Chapter 4 A Calibration-Free SAR ADC Array for Touch Sensing Applications 49
1 Introduction 49
2 Architecture of the Proposed SAR ADC 50
3 Mismatch Mitigation Techniques 53
3.1 DAC Capacitor Mismatch 53
3.2 Comparator Offset Mismatch 56
3.3 Gain Mismatch 61
4 Key Circuit Building Blocks 66
4.1 Bootstrapped Switch 66
4.2 Comparator 67
4.3 Digital Control Logic Circuit 70
4.4 Reference Buffer 72
4.5 CDAC Array 73
4.6 Digital Error Correction Decoder 76
4.7 LVDS 77
Chapter 5 Simulation and Measurement Results 79
1 Layout Floor Plan 79
2 Simulation Results 82
3 Chip Micrograph and Measurement Setup 83
4 Measurement Results 88
Chapter 6 Conclusion and Future Work 103
1 Conclusion 103
2 Future Work 104
Bibliography 106
                                    

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