在超寬頻的應用下，我們提出一個採用新型快閃摺疊式架構的低功率高速類比數位轉換器設計。使用台積電 0.18 微米製程下線，驗證一個五位元每秒十億次取樣類比數位轉換器。此新型架構結合了快閃式以及摺疊式類比數位轉換器的特徵，前端架構是與傳統快閃式轉換器的前端架構相同，並且使用電流式多工器取代摺疊放大器，以得到循環式溫度計碼，且減緩了頻率加乘效應。採用此一架構，比較器的數目只要傳統架構的一半，其具有較小電路面積與降低輸入阻抗優點。模擬結果顯示，在取樣頻率為每秒十億次，輸入頻率趨近Nyquist rate時，擁有4.25的有效位元。除此之外，差分非線性誤差和積分非線性誤差分別小於0.175以及0.261最小位元。所消耗的功率為69 mW，每一次的資料轉換所消耗的能量約為2.23 pJ.

For multi-band OFDM UWB applications, we propose a new architecture, which combines the characteristics of flash and folding structures, for low-power high-speed analog-to-digital conversion. The analog front-end of the proposed design is the same as that of a typical flash A/D converter. By replacing folding amplifier with current-mode multiplexer (MUX), cyclic thermometer output codes, the digital output codes of a conventional folding A/D converter, can be obtained. By manipulating this arrangement, the frequency multiplication problem of a traditional folding amplifier is alleviated. Using the proposed architecture, the number of the comparators is reduced to 16, and it is 32 for a typical flash A/D converter. A 5-bit 1-Gsample/s A/D converter is designed in TSMC 0.18-m 1P6M CMOS process. Operating at 1-GSample/s, the ENOB is 4.25 bits at input frequency 500 MHz. The maximum DNL is no more than 0.175 LSB and the maximum INL is less than 0.261 LSB. This A/D converter consumes 69 mW from a 1.8 V supply voltage, achieving an FOM of 2.23 pJ/ conversion-step at 1-GSample/s.

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