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研究生： 陳宗煥
Chen, Tsung-Huan
論文名稱： 低功率逐漸趨近式類比數位轉換器設計
Successive Approximation Architecture for Low-Power A/D Converter
指導教授： 劉濱達
Liu, Bin-Da
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2009
畢業學年度： 97
語文別： 英文
論文頁數： 68
中文關鍵詞： 被動式電荷重新分布 、雙倍取樣 、連續漸進式類比數位轉換器
外文關鍵詞： double sampling, SAR ADC, passive charge sharing
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    • 本論文內容實現了兩個連續漸進式類比數位轉換器。第一個架構中，完成了一個應用在高畫質數位電視系統上的類比數位轉換器。我們使用簡單的靴帶式技巧在取樣電路上，確保訊號在前級所需的解析度。此外，此設計同時使用了PMOS和NMOS作為比較器的輸入差動對，使得輸入訊號範圍可以到達軌對軌。在此實驗中，利用 TSMC 0.18 微米的製程，實現一個供應電壓為1.8 V，輸出為8位元的數位訊號，取樣頻率為每秒五千四百萬次的類比數位轉換器。實驗結果顯示，在輸入訊號為 1 MHz 時，其訊號對雜訊及諧波失真比為 49.1 dB，整體功率消耗為 1.8 mW.每次轉換所需要的平均能量約為 140 fJ。
    在第二個架構中，我們應用雙倍取樣的技巧在前端取樣電路，其結果不僅可以改善傳統被動式電荷重新分布架構中，取樣訊號範圍衰減的缺點，還可縮小輸入端取樣電容的大小，減少額外的面積，更可以降低比較器原本所需要的精確度，進而減少功率消耗。此架構我們使用TSMC 0.13 微米的製程來設計，供應電壓為1.2 V。在輸入訊號為 1 MHz 時，輸出為8位元的數位訊號，取樣頻率為每秒兩千萬次的類比數位轉換器。其訊號對雜訊及諧波失真比為 48 dB，整體功率消耗為 150 W，每次轉換所需要的平均能量約為 36 fJ。

    Two successive approximation analog-to-digital converters are presented in this thesis. In the first architecture, a converter that meets the specification of HDTV system is implemented. We use simple boot-strapped technique in sample-and-hold to ensure the quality of sampled signal is above specification while still has sufficient bandwidth. Besides, both PMOS and NMOS are adopted in the input differential pairs of the comparator to guarantee the input signal range could reach rail-to-rail. The experimental results of the first converter, an 8-bit 54 MS/s SAR ADC, show that the total power consumption is 1.8 mW by using TSMC 0.18-m process. The signal-to-noise and distortion ratio (SNDR) is 49.1 dB with 1 MHz input frequency and the figure-of-merit (FOM) is only 140 fJ/conversion-step.
    In the second architecture, we employ double sampling technique in the front-end track-and-hold. This not only improves the drawback of reduced input signal range as in the conventional passive charge sharing architecture, but halves the size of sampling capacitor, thus greatly decreases the silicon area and certain unnecessary power wasting. The experimental results of the second converter, an 8-bit 20 MS/s SAR ADC, show that the total power consumption is 150 W. The SNDR is 48 dB with 1 MHz input frequency and the FOM of pre-layout simulation is 36 fJ by using TSMC 0.13-m process which is comparable with the current state-of-the-art inventions.

    Abstract x Contents xii List of Tables xiv List of Figures xv Chapter 1 Introduction 1 1.1 Introduction 1 1.2 Thesis Organization 2 Chapter 2 The Fundamentals of Analog-to-Digital Converter 5 2.1 Introduction of ADCs 5 2.2 Specifications 7 2.2.1 Static specifications 7 2.2.2 Dynamic specification 12 2.3 Architectures of Analog-to-Digital Converter 13 2.3.1 Flash ADC 14 2.3.2 Pipelined ADC 15 2.3.3 Cyclic ADC 17 2.3.4 Successive approximation ADC 18 Chapter 3 An 8-bit 54 MS/s Successive Approximation A/D Converter 21 3.1 Motivation 21 3.2 The Architecture of SAR A/D Converter 22 3.2.1 Sample and hold 23 3.2.2 Comparator 27 3.2.3 DAC array 29 3.2.4 Digital control circuit 30 3.3 Simulation Results 31 3.3.1 Functional simulation 31 3.3.2 Pre-layout simulation results 32 3.4 Layout Consideration 37 3.5 Performance Comparison 38 Chapter 4 Passive Charge-Sharing Successive Approximation A/D Converter with Double Sampling Technique 41 4.1 Motivation 41 4.2 The Conventional Architecture of Passive 42 Charge Sharing SAR ADC 42 4.2.1 Track and hold 42 4.2.2 Capacitor array 43 4.3 The Proposed Architecture of Passive Charge-Sharing SAR ADC 47 4.3.1 Track and hold 48 4.3.2 Capacitor array 50 4.3.3 Comparator 52 4.4 Simulation Results 53 4.4.1 Functional simulation 53 4.4.2 Pre-layout simulation results 54 4.5 Performance Comparison 57 Chapter 5 Conclusions and future Work 59 5.1 Conclusions 59 5.2 Future Work 60 References 61

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