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研究生： 黃冠穎
Huang, Guan-Ying
論文名稱： 有效利用能量的逐漸趨近式類比數位轉換器設計
Design of Energy Efficient Successive-Approximation Analog-to-Digital Converter
指導教授： 張順志
Chang, soon-Jyh
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2007
畢業學年度： 95
語文別： 英文
論文頁數： 60
中文關鍵詞： 逐漸趨近式類比數位轉換器 、類比數位轉換器 、有效利用能量
外文關鍵詞： successive approximation ADC, successive approximation analog-to-digital conve, energy efficient, SAR ADC
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    • 本論文主要實現了兩個逐漸趨近式類比數位轉換器。在第一個轉換器中，我們利用調整開關的數量大小來得到新的電阻電容時間常數，藉以提升類比數位轉換器的速度。此外，此一設計使用自我時間控制的方法去控制比較器，這樣可以節省一半左右的功率消耗。實驗結果顯示，利用TSMC 0.13 μm的製程，這個8位元每秒取樣兩千七百萬次的逐漸趨近式類比數位轉換器平均消耗功率為385 μW，每次轉換所消耗的平均能量約為105 fJ。
    於第二個轉換器中，我們採用新的電容串架構，再加上被動式電荷重新分布的機制來提升轉換器的速度，同時降低電容串部分的功率消耗，而且在轉換器輸入端的電容值也可以明顯的減小。這個8位元每秒取樣五千萬次的被動式電荷重新分布逐漸趨近式類比數位轉換器同樣利用TSMC 0.13 μm的製程來進行設計，平均消耗功率為294 μW，每次轉換所消耗平均能量約為41 fJ。

    In this thesis, two successive-approximation (SAR) analog-to-digital converters (ADCs) are proposed. In the first ADC, a novel RC time constant capacitor array, which adjusts the numbers of switch, is used to speed up the conversion rate. And a self timing controller is used to control the comparator, which can save half of the power consumption of the comparator. Simulation results of the first ADC, an 8-bit 27 MS/s SAR ADC, show that the total power consumption is 385 μW and the average energy consumption per conversion step is 105 fJ in the TSMC 0.13 μm process.
    In order to further increase the conversion rate, a novel capacitor array with passive charge-sharing (PCS) technique, which can effectively reduce the total power consumption and the input capacitance, is used in the second ADC. Simulation results of the second ADC, an 8-bit 50 MS/s PCS SAR ADC, show that the total power consumption is 294 μW and the average energy consumption per conversion step is 41 fJ in the TSMC 0.13 μm process.

    Abstract List of Figures List of Tables Chapter 1 Introduction 　1.1 Motivation 01 　1.2 Energy Efficient of Conventional ADCs 02 　1.3 Thesis Organization 03 Chapter 2 The Principle and Architectures of Successive Approximation A/D Converters 　2.1 Principle of Successive Approximation Algorithm 05 　2.2 The Architecture of Successive Approximation ADC 07 　　2.2.1 DAC-Based Successive Approximation 07 　　2.2.2 Unipolar Charge-Redistribution A/D 07 　　2.2.3 Signed Charge-Redistribution A/D with a Single Reference Voltage 11 　2.3 Capacitive Digital-to-Analog Converter 14 　　2.3.1 Binary-Weighted Capacitor Array 14 　　2.3.2 C-2C Capacitor Array 15 　　2.3.3 Pseudo C-2C Capacitor Array 16 　2.4 Latched Comparator 18 　　2.4.1 Static Latched Comparator 19 　　2.4.2 Class-AB Latched Comparator 20 　　2.4.3 Dynamic Latched Comparator 21 Chapter 3 An 8-Bit 27MS/s Successive Approximation A/D Converter 　3.1 Motivation 22 　3.2 The Architecture of Proposed Successive Approximation A/D Converter 23 　　3.2.1 Sample and Hold 25 　　3.2.2 Comparator with Rail-to-Rail Range 25 　　3.2.3 Digital-to-Analog Converter (DAC) 28 　3.3 Simulation Results 30 　　3.3.1 Functional simulation 30 　　3.3.2 Pre-Layout Simulation Result 31 　　3.3.3 Post-Layout Simulation Result 35 Chapter 4 Energy Efficient Passive Charge-Sharing (PCS) Successive Approximation A/D Converter 　4.1 Motivation 40 　4.2 The Architectures of Conventional Passive Charge-Sharing SAR ADC 41 　　4.2.1 Capacitor Array 43 　　4.2.2 Comparator 44 　　4.2.3 Digital Control Circuit 45 　4.3 The Architectures of Proposed Passive Charge-Sharing SAR ADC 46 　　4.3.1 Capacitor Array 48 　　4.3.2 Comparator 49 　　4.3.3 Digital Control Circuit 51 　4.4 Simulation Results 52 　　4.4.1 Functional Simulation 52 　　4.4.2 Pre-Layout Simulation 53 Chapter 5 Conclusion and Future Works 　5.1 Conclusion 56 　5.2 Future Works 57 Reference

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