本論文實現了捲積神經網路(CNN)硬體加速器設計。隨著時代發展，人工智能已然成為目前熱門的研究領域，其中捲積神經網路是目前深度神經網路(Deep Neural Network, DNN)領域的發展主力，但也存在通量和能量消耗的挑戰，藉由探討捲積運算中的重用性，設計空間探索，硬體間管線化設計等，做為我們的硬體加速器設計方案。
在傳統類神經網路的基礎上，捲積神經網路是其中一種發展出來的機器學習模型。但由於在捲積神經網路其中，有著大量的乘加運算，而為了加速運算，有很多種不同的重用設計方式，不同的重用方式的硬體設計都要經過長時間的分析並重新分析硬體。因此藉由高階合成(High-Level Synthesis, HLS)工具將C語言實現快速的轉換為硬體描述語言，快速實現並生成可用的捲積神經網路硬體加速器。
設計硬體加速器方面，我們藉由代入實際CNN參數例子，分析各個Local Buffer大小之可能性，經過排列組合後，透過記憶體訪問次數、計算單元執行次數及整體執行時間，假設並推導設計公式，且成立目標式代入設計公式後，可找到當中最佳Local Buffer大小；而後以此Local Buffer為基礎下，分析計算各模組之運行處理時間，找到各模組中最佳的Pipeline Latency(ii)之執行，並在模組中實現硬體管線化設計。而在整體架構上，我們利用雙緩衝器(Double-Buffer)之設計，並搭配HLS工具生成硬體架構，在此架構能以達到整體資料流之優化，最終實現任務級(Task-Level)資料流管線化設計。

This paper implements the convolutional neural network (CNN) hardware accelerator design. With the development of the times, artificial intelligence has become a popular research field at present. Among them, convolutional neural network is the main force in the development of deep neural network (DNN) field, but there are also challenges of flux and energy consumption. By discussing the reusability of convolution operations, design space exploration, pipeline design between hardware, etc., as our hardware accelerator design.
On the basis of traditional neural network, convolutional neural network is one of the developed machine learning models. However, because there are a large number of multiplication and addition operations in the convolutional neural network, and in order to speed up the operation, there are many different reuse design methods, and the hardware design of different reuse methods must be analyzed and reanalyzed for a long time body. Therefore, a high-level synthesis (HLS) tool is used to quickly convert the C language implementation into a hardware description language, and quickly implement and generate a usable convolutional neural network hardware accelerator.
In terms of designing hardware accelerators, we analyze the possibility of the size of each Local Buffer by substituting the actual CNN parameter examples. After permutation and combination, the design formula is assumed and deduced based on the number of memory accesses, the number of execution times of the computing unit and the overall execution time. After establishing the target formula and substituting it into the design formula, the optimal Local Buffer size can be found. Then, based on this Local Buffer, analyze the execution time of each module, find the best implementation of Pipeline Latency(ii) in each module, and implement the hardware pipeline design in the module. In the overall architecture, we use the Double-Buffer design, and with the HLS tool to generate the hardware architecture, this architecture can achieve the optimization of the overall dataflow, and finally achieve the task-level Dataflow pipeline design.

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