簡易檢索 / 詳目顯示

研究生: 黃啟睿
Huang, Chi-ray
論文名稱: 操作於次臨界電壓區域且可容忍製程變異的相關器設計與實現
Design and Implementation of a Variation Insensitive Sub-threshold Correlator
指導教授: 邱瀝毅
Chiou, Lih-Yih
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2009
畢業學年度: 97
語文別: 英文
論文頁數: 67
中文關鍵詞: 相關器次臨界電壓數位電路設計製程變異電壓準位轉換器
外文關鍵詞: Sub-threshold operation, Process variation, Level converter, Correlator
相關次數: 點閱:100下載:1
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報
  • 現今新興的超低功率消耗的應用,像是無線感測系統等,越來越受到大家的關注與重視。為了能夠達到超低功率消耗的需求,以延長產品的使用時間,次臨界電壓數位電路設計便成為一個新興且可行的方法之一。在本篇論文裡,我們使用在基頻處理器中一個重要的運算單元,也就是相關器,作為我們主要的數位電路設計,以表現電路能夠支援大範圍操作電壓調整(從高於臨界電壓區域,乃至於次臨界電壓區域)的可行性。一個出現於次臨界電壓電路設計的重要問題,便是製程變異對電路效能的敏感性與影響大大地增加。為了能夠降低製程變異的影響,我們從電路結構的設計上來解決此問題,取代一般常見會消耗大量面積的基底偏壓技術。為了使得操作於次臨界電壓區域的電路與高於臨界電壓區域的電路能夠正確地溝通,我們便設計了一個新的且能夠有效地轉換次臨界電壓訊號到高於臨界電壓訊號的電壓準位轉換器。在本篇論文中,相關器與電壓準位轉換器皆使用UMC 90nm的製程技術設計電路。根據模擬的結果可知,次臨界電壓相關器電路可正確地操作於200mV的供應電壓,並且提供40MHz的效能,同時僅消耗22uW的功率。然而,此相關器不但可以操作在200mV到1V的供應電壓範圍,還能夠在供應電壓為1V時,提升效能達到800MHz,同時消耗5.7mW的功率。

    The emerging applications such as wireless sensor networks demanding for ultra low power consumption to prolong operating time without changing batteries are getting more and more attentions. Digital sub-threshold circuit design has become a viable method to achieve ultra low power consumption requirements. In this thesis, the correlator, one major component of the baseband receiver, is used to demonstrate the feasibility of operating at sub-threshold to super-threshold supply range. The increasing sensitivities of the process variations at sub-threshold region are minimized using circuit structures instead of body biasing which consumes large area overhead. A novel level converter that can efficiently convert the sub-threshold input signals to super-threshold signals is also proposed and integrated with the sub-threshold correlator. The correlator implemented using 90nm technology can operate at 200mV with 40MHz and consumes only 22 W. The correlator not only can operate with supply voltage from 0.2V to 1V, but also can scale up the performance to 800MHz at 1V and consumes 5.7mW.

    Chapter 1 Introduction...............1 1.1 Motivation..................1 1.1.1 Sub-threshold Designs.......1 1.1.2 Ultra Low Power Correlator..3 1.2 Contributions...............4 1.3 Thesis Overview.............5 Chapter 2 Sub-threshold Logic Circuit Designs..5 2.1 Sub-threshold Operations....6 2.2 Process Variations..........9 2.2.1 Sources of Process Variation.....9 2.2.2 Impact of Process Variations.....10 2.3 Interface between Sub-threshold and Super-threshold Design...........................11 2.3.1 Necessity of Level Converter......12 2.3.2 Conventional Level Converters & Issues for Sub-threshold logic.............................13 2.4 Recent Works.......................17 2.4.1 Sub-threshold Circuit Design.......17 2.4.2 Level Converter for Sub-threshold Logics....20 Chapter 3 Sub-threshold Correlator Design....23 3.1 System Architecture Overview........23 3.2 Correlator Unit Design..............26 3.2.1 Proposed Sub-threshold Full Adder Design....26 3.2.2 Two Stages Pipelined Correlator.....31 3.3 Peripheral Circuits.................35 3.3.1 Proposed Level Converter for Sub-threshold Designs.......................................36 3.3.2 Output Multiplexing Scheme...........39 3.3.3 Frequency Divider....................40 Chapter 4 Simulation Results..................41 4.1 Simulation Results of Sub-threshold FA Circuit .....................................41 4.2 Simulation Results of Proposed Level Converter Design for Sub-threshold Logics...............47 4.3 Simulation Results of Sub-threshold correlator .....................................53 4.4 Layout View..........................59 Chapter 5 Conclusions and Future Works........61 5.1 Conclusions..........................61 5.2 Future Works.........................62 Reference .....................................63 Appendix (Chip Implementation)................67

    [1] B. H. Calhoun, D. C. Daly, N. Verma, D. F. Finchelstein, D. D. Wentzloff, A. Wang, S. H. Cho and A. P. Chandrakasan, “Design considerations for ultra-low energy wireless micro-sensor nodes,” IEEE Trans. on Computers, Vol. 54, No. 6, pp. 727-740, Jun. 2005.
    [2] S. Hanson, B. Zhai, K. Bernstein, D. Blaauw, A. Bryant, L. Chang, K. K. Das, W. Haensch, E. J. Nowak and D. M. Sylvester, “Ultra Low Voltage Minimum Energy CMOS, ” IBM J. of Research & Development, Vol. 50, no. 4/5, July. 2006.
    [3] L. S. Y. Wong, S. Hossain, A. Ta, J. Edvinsson, D. H. Rivas and H. Naas, “A very low-power CMOS mixed-signal IC for implantable pacemaker applications,” IEEE J. of Solid-State Circuits, Vol. 39, No. 12, pp. 2446-2456, December 2004.
    [4] K. Sunyoung, C. Namjun, S. J. Song, D. Kim, K. Kim and H. J. Yoo, ”A 0.9-V 96-/spl mu/W Digital Hearing Aid Chip with Heterogeneous S-D DAC,” in Proc. IEEE VLSI Circuits Symposium, pp. 55-56, 2006.
    [5] B. Gyselinckx, C. V. Hoof, J. Ryckaert, R. F. Yazicioglu, P. Fiorini and V. Leonov, “Human++: autonomous wireless sensors for body area networks,” in Proc. IEEE Custom Integrated Circuits Conference, pp. 13-19, 2005.
    [6] A. Wang, A. P. Chandrakasan, and S. V. Kosonocky, “Optimal supply and threshold scaling for sub-threshold CMOS circuits,” in Proc. IEEE Computer Society Annual Symposium on VLSI, pp. 5–9, 2002.
    [7] J. Chen, L. T. Clark, and T. Chen, “An Ultra-Low-Power Memory With a Sub-threshold Power Supply Voltage,” IEEE J. of Solid-State Circuits, Vol. 41, No. 10, pp.2344-2353, October 2006.
    [8] K. Roy, J. P. Kulkarni, and M. E. Hwang, ”Process-Tolerant Ultralow Voltage Digital Sub-threshold Design,” in Proc. IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, pp.42-45, Jan. 2008.
    [9] J. Chen, L. T. Clark, and Y. Cao, “Ultra-low voltage circuit design in the presence of variations,” IEEE Circuits and Devices Mag. pp. 12–20, Jan. 2006.
    [10] A. Wang and A. P. Chandrakasan, “A 180-mV sub-threshold FFT processor using a minimum energy design methodology,” IEEE J. of Solid-State Circuits, Vol. 40, No. 1, pp. 310-319, 2005.
    [11] A. Raychowdhury, B. C. Paul, S. Bhunia and K. Roy, “Computing with sub-threshold leakage: device/circuit/architecture co-design for ultra low power sub-threshold operation,” IEEE Trans. on Very Large Scale Integration Systems, Vol. 13, No. 11, pp. 1213-1224, 2005.
    [12] N. S. Kim, T. Kgil, K. Bowman, V. De, and T. Mudge, “Total power optimal pipelining and parallel processing under process variations in nanometer technology,” in Proc. International Conference on Computer-Aided Design, pp. 535–540, 2005.
    [13] J. W. Tschanz, J. T. Kao, S. G. Narendra, R. Nair, D. A. Antoniadis, A. P. Chandrakasan and V. De, “Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage,” IEEE J. of Solid-State Circuits, Vol. 37, No, 11, pp. 1396-1402, 2002.
    [14] Tschanz, J., K. Bowman and V. De, “Variation-tolerant circuits: circuit solutions and techniques,” in Proc. of 42nd Annu. Design Automation Conference, pp. 762-763, 2005.
    [15] G. Ono and M. Miyazaki, “Threshold-voltage balance for minimum supply operation, “IEEE J. of Solid-State Circuits,” Vol. 38, No. 5, pp. 830-833, 2003.
    [16] Yu Pu, H. Corporaa, J. P. d. Gyvez and Y. Ha, “VT Balancing and Device Sizing toward High Yield of Sub-threshold Static Logic Gates,” in Proc. International Symposium on Low Power Electronics and Design, pp.355-358, August 2007.
    [17] B. H. Calhoun and A. P. Chandrakasan, “A 256-kb 65-nm Sub-threshold SRAM Design for Ultra-Low-Voltage Operation,” IEEE J. of Solid-State Circuits, Vol. 42, No. 3, pp. 680-688, March 2007.
    [18] Z. Bo, D. Blaauw, D. Sylvester and S. Hanson “A Sub-200mV 6T SRAM in 0.13um CMOS,” in Proc. IEEE International Solid-State Circuits Conference, pp. 332-606, February 2007.
    [19] M. Zhang, J. Gu, and C. H. Chang, “A novel hybrid pass logic with static CMOS output drive full-adder cell,” in Proc. IEEE International Symposium on Circuits and Systems, pp. 317–320, 2003.
    [20] S. Goel, A. Kumar and M. A. Bayoumi, “Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style,” IEEE Trans. on Very Large Scale Integration Systems, Vol.14, No.12, pp.1309-1321, 2006.
    [21] V. Sze and A. P. Chandrakasan, “A 0.4-V UWB Baseband Processor,” in Proc. International Symposium on Low Power Electronics and Design, pp. 262-267, 2007.
    [22] I. J. Chang, K. Jae-Joon, and K. Roy,” Robust Level Converter Design for Sub-threshold Logic,” in Proc. International Symposium on Low Power Electronics and Design, pp. 14-16, 2006.
    [23] S. Hui and T. Chi-Ying, “A robust, input voltage adaptive and low energy consumption level converter for sub-threshold logic,” in Proc. European Solid State Circuits Conference, pp. 312-315, 2007.
    [24] B. Zhai, S. Pant, S. Hanson, J. Olson, A. Reeves, M. Minuth, R. Helfand, T. Austin, D. Sylvester, and D. Blaauw, “Energy-Efficient Sub-threshold Processor Design,” IEEE Trans. on Very Large Scale Integration Systems, Vol. 17, No. 8, pp. 1127-1137, August 2009.
    [25] A. Chavan, and E. MacDonald, “Ultra Low Voltage Level Shifters to Interface Sub and Super Threshold Reconfigurable Logic Cells,” in Proc. IEEE Aerospace Conference, pp. 1-6, 2008.
    [26] F. Fallah and M. Pedram, “Standby and Active Leakage Current Control and Minimization in CMOS VLSI Circuits,” IEICE Trans. on electronics, Vol.E88–C, No.4, 2005.
    [27] Neil H.E. Weste and David Harris, “CMOS VLSI Design: A Circuits and Systems Perspective, 3rd edition”, Addison Wesley, 2004, ISBN:0321149017

    下載圖示 校內:2014-09-09公開
    校外:2014-09-09公開
    QR CODE