簡易檢索 / 詳目顯示

研究生: 張峻豪
Chang, Chun-How
論文名稱: 針對通用圖形處理器的智能熱管理方法
An Intelligent Thermal Control Method for General-Purpose Graphic Processing Units
指導教授: 邱瀝毅
Chiou, Lih-Yih
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2020
畢業學年度: 108
語文別: 中文
論文頁數: 60
中文關鍵詞: 邊緣運算裝置通用計算圖形處理器動態電壓頻率調整熱管理
外文關鍵詞: Edge Computing Devices, GPGPU, Dynamic Voltage and Frequency Scaling (DVFS), Thermal Management
相關次數: 點閱:151下載:0
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報
  • 隨著物聯網(Internet of Thing, IoT)的成熟與5G通訊等技術的成長,邊緣運算(Edge computing)的概念逐漸受到重視,許多相關應用如機械手臂、自駕車、擴增實境(AR, augmented reality)等等也開始受到關注,由於這些應用特別強調即時的影像分析及影像辨識處理的能力,因此通用計算圖形處理器開始被廣泛的應用在這些工作上,然而大量的運算單元必然存在著相當高的功率消耗,在邊緣裝置朝著更小巧,功能更強大的應用發展趨勢下,高功率密度帶來的高溫效應逐漸受到關注,由於晶片開發早期難以獲取晶片功率與溫度等資訊,因而導致很高的熱複雜性被忽視的風險,使得許多熱議題在開發晚期才逐漸顯露。在這樣的背景之下,勢必需要結合更強大精準的熱建模以及更有效的熱管理技術才能克服這樣的挑戰。
    本論文提出了一種針對通用計算圖形處理器的智能熱管理方法,在這個方法中會搭配功率與熱建模來獲取及時的溫度資訊,並針對通用計算圖形處理器內的每顆核心進行調整,進而讓處理器在維持一定的效能下亦可運作在安全的溫度內,實驗結果顯示,本論文所提出的方法與一般熱管理的演算法相比,整體而言平均可以降低約13.6%的峰值溫度,同時只付出約1.1%的效能代價與1.3%的能量消耗。

    With the growth of Internet of Thing (IoT), the concept of edge computing is gaining popularity. Because many related applications focus on image processing or image recognition, the general-purpose computing on graphics processing units (GPGPUs) nowadays are widely used on mobile and edge devices because of its strong computing capability. However, with the increasing power density on limited devices volume, thermal issues become critical. High power density may generate serious thermal effects and the heat issues of chips cannot be ignored. Therefore, when designing a GPGPU for mobiles and edge computing devices, thermal management has become one of the main issues.
    The thesis proposes an intelligent thermal control method for GPGPUs with low power techniques and task schedule. The proposed scheme can detect the temperature of each single instruction multiple thread (SIMT) core and dynamically adjust the voltage and frequency of different clusters of cores to reduce the peak temperature during runtime. According to the experimental results, when compared with the baseline approach, the proposed design can reduce temperature by 13.6% with merely 1.1% performance overhead and 1.3% energy overhead on average.

    目錄 摘 要 i 致 謝 vi 目錄 vii 表目錄 ix 圖目錄 x 第 1 章 緒論 1 1.1 研究背景 1 1.1.1 邊緣運算 1 1.1.2 通用計算圖形處理器 2 1.1.3 功率消耗對溫度之影響與相關熱管理 3 1.2 研究動機 4 1.3 研究貢獻 5 1.4 論文架構 5 第 2 章 相關研究背景 6 2.1 通用計算圖形處理器整體架構 6 2.2 功率消耗之來源介紹與動態熱管理技術簡介 8 第 3 章 相關文獻探討 12 3.1 通用計算圖形處理器之功率管理 12 3.1.1 關鍵功率路徑分析 12 3.2 通用計算圖形處理器之相關動態熱管理 15 3.2.1 應用於多核心系統之具溫度感知之工作排程技術 15 3.2.2 應用於移動裝置平台之動態熱預測與功率管理技術 17 3.2.3 應用於多核心系統之混合式動態熱管理技術 18 3.3 相關文獻總結 21 第 4 章 應用於通用計算圖形處理器的動態熱管理方法 23 4.1 問題描述 23 4.2 目標平台之環境與架構 24 4.2.1 平台介紹 24 4.2.2 多重串流處理器內部架構 26 4.2.3 功率模型 29 4.2.4 熱模擬引擎 31 4.3 動態熱管理機制 33 4.3.1 熱溫差平衡機制 33 4.3.2 考量工作負載之動態閾值機制 36 4.3.3 工作排程機制 41 4.3.4 動態熱管理之流程圖 43 第 5 章 實驗結果與分析 44 5.1 實驗環境設置 44 5.2 實驗結果 46 5.2.1 不加入閾值限制之溫度管理比較 47 5.2.2 加入閾值之溫度管理比較 50 5.3 額外硬體付出 54 第 6 章 結論和未來工作 55 6.1 結論 55 6.2 未來工作 56 參考文獻 57

    [1] Y. Hengzhou, G. Yang, and M. Zhuo, “A 40nm/65nm process adaptive low jitter phase-locked loop,” in Proc. 2014 International Symposium on Integrated Circuits (ISIC), 2014, pp. 500–503.
    [2] Y. H. J. Shi, E. Soenen, and A. R. and J. Gaither, “A wide-range DC/DC converter with 2ndorder digital compensation and direct battery connection in 40nm CMOS,” in Proc. IEEE Cust. Integr. Circuits Conf., 2011, pp. 1-4.
    [3] E. Fernandes, “Internet of Things Market Size, Growth | IoT Industry Report [2020-2027].”https://www.fortunebusinessinsights.com/industry-reports/internet-of-things-iot-market-100307.
    [4] C. -P. Chang, “An Energy-Efficient General-Purpose Computing on GPU for Edge Computing Devices Using Hardware Runtime Utilization,” M.S. thesis, Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan, 2019.
    [5] M. S. Mohammed, A. K. Al-Dhamari, A. A. H. Ab Rahman, N. Paraman, A. A. M. Al-Kubati, and M. N. Marsono, “Temperature-aware task scheduling for dark silicon many-core system-on-chip,” in Proc. 2019 8th International Conference on Modeling Simulation and Applied Optimization (ICMSAO), Manama, Bahrain, Apr. 2019.
    [6] G. Singla, G. Kaur, A. K. Unver, and U. Y. Ogras, “Predictive Dynamic Thermal and Power Management for Heterogeneous Mobile Platforms,” in Proc. -Design, Autom. Test Eur. DATE, Apr. 2015, vol. 2015-April, pp. 960–965.
    [7] P. -H. Yang, “Hybrid DTM for Multi-Core System using Advanced Heterogeneous Package,” M.S. thesis, Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan, 2018.
    [8] K. -C. Hsu, “Performance Prediction Model on HSA-Compatible General-Purpose GPU System,” M.S. Thesis, Department of Institute of Computerand Communication Engineer,National Cheng Kung University, Tainan, Taiwan, 2016.
    [9] V. Lakshminarayanan and N. Sriraam, "The effect of temperature on the reliability of electronic components," in Proc. 2014 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT), Bangalore, 2014, pp. 1-6.
    [10] S. Kalra, “Effect of temperature dependence on performance of digital CMOS circuit technologies,” in Proc. 2013 INTERNATIONAL CONFERENCE ON SIGNAL PROCESSING AND COMMUNICATION (ICSC) , Noida, 2013, pp. 392-395,
    [11] H. Sultan, “Is Leakage Power a Linear Function of Temperature? | DeepAI.” https://deepai.org/publication/is-leakage-power-a-linear-function-of-temperature
    [12] D. Cuesta, J. L. Risco-Martín, J. L. Ayala, and J. I. Hidalgo, “Thermal-aware floorplanner for 3D IC, including TSVs, liquid microchannels and thermal domains optimization,” Appl. Soft Computing, vol. 34, pp. 164–177, Sep.2015.
    [13] S. K. Srivathsa, V. B. Suresh, P. Panchapakeshan, and S. Kundu, “Dynamic thermal management for system-on-chip using bus arbitration,” in Proc. 2010 International SoC Design Conference. Seoul, 2010, pp. 372-375,
    [14] A. Kumar, L. Shang, L. S. Peh, and N. K. Jha, “System-Level Dynamic Thermal Management for High-Performance Microprocessors,” IEEE Trans. Comput. Des. Integr. Circuits Syst., vol. 27, no. 1, pp. 96–107, Jan.2008.
    [15] B. Salami, M. Baharani, and H. Noori, “An adaptive temperature threshold schema for dynamic thermal management of multi-core processors,” in Proc. - 17th CSI Int. Symp. Comput. Archit. Digit. Syst. CADS 2013, 2013, pp. 119–120.
    [16] W. -S. Hsieh, “Design of Cycle-accurate SIMT Core and Implementation,” M.S. Thesis, Department of Institute of Computerand Communication Engineer, National Cheng Kung University, Tainan, Taiwan, Tainan, Taiwan, 2016.
    [17] J. -H. Jheng, “Micro-Architecture Optimization of HSA-Compatible GPU,” M.S. thesis, Department of Institute of Computerand Communication Engineer, National Cheng Kung University, Tainan, Taiwan, Tainan, Taiwan, 2018.
    [18] L. Liu and D. Qi, “An Independent Task Scheduling Algorithm in Heterogeneous Multi-core Processor Environment,” in Proc. 2018 IEEE 3rd Adv. Inf. Technol. Electron. Autom. Control Conf. IAEAC 2018, Dec. 2018, pp. 142–146.
    [19] G. Wu, Z. Xu, Q. Xia, J. Ren and F. Xia, "Task Allocation and Migration Algorithm for Temperature-Constrained Real-Time Multi-Core Systems," in Proc. 2010 IEEE/ACM Int'l Conference on Green Computing and Communications & Int'l Conference on Cyber, Physical and Social Computing, Hangzhou, 2010, pp. 189-196.
    [20] J. Cha, J. Kim, and Y. Park, “Core-level DVFS for Spatial Multitasking GPUs,” in Proc. IEEE Reg. 10 Annu. Int. Conf. (TENCON), Feb. 2019, vol. 2018-October, pp. 1525–1528.
    [21] M. H. Vo, “The Merged Clock Gating Architecture for Low Power Digital Clock Application on FPGA,” in Proc. Int. Conf. Adv. Technol. Commun., Dec. 2018, vol. 2018-October, pp. 282–286.
    [22] G. Bhargave, S. Uniyal, and P. Sheokand, “Low Power Adiabatic 4-Bit Johnson Counter Based on Power-Gating Cpal Logic,” in Proc. 2nd IEEE Int. Conf. Innov. Appl. Comput. Intell. Power, Energy Control. with their Impact Humanit. CIPECH 2016, May 2017, pp. 297–301.
    [23] B. Yu, S. Dong, and S. Goto, “Multi-Voltage and Level-Shifter Assignment Driven Floorplanning,” in ASICON 2009 - Proc. 2009 8th IEEE Int. Conf. ASIC, 2009, pp. 1264–1267.
    [24] “JEDEC STANDARD.” http://www.softnology.biz/pdf/JESD79-4_DDR4_SDRAM.pdf?fbclid=IwAR1doOEVrs8Y6UK3JsNjaiUs9gvu1OhXSxNVUjVbKFAc8kxROPRAAN8T58A (accessed Jul. 15, 2020).
    [25] W. -X. YANG, “Fast and Effective Thermal Analysis for Integrated Circuits Using 3-Dimensional Discontinuous Galerkin Method,” M.S. thesis, Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan, 2019.

    無法下載圖示 校內:2025-08-25公開
    校外:不公開
    電子論文尚未授權公開,紙本請查館藏目錄
    QR CODE