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研究生： 劉彥廷
Liu, Yen-Ting
論文名稱： 低功率高速類比數位轉換器
Low-Power High-Speed Analog-to-Digital Converters
指導教授： 張順志
Chang, Soon-Jyh
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2006
畢業學年度： 94
語文別： 英文
論文頁數： 113
中文關鍵詞： 低功率 、高速 、類比數位轉換器
外文關鍵詞： analog-to-digital converter, low power, high speed
相關次數： 點閱：161  下載：10 
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    • 在超寬頻的應用下，我們提出二個低功率高速類比數位轉換器的設計。第一個設計是一個五位元每秒十億次取樣快閃式類比數位轉換器，使用台積電 0.18 微米製程下線驗證。量測結果顯示在六億的取樣頻率下，有效位元數為四位元，而且消耗功率為 60 mW。第二個設計是一個六位元每秒十億次取樣類比數位轉換器，使用台積電 0.13 微米製程。我們使用二階式次範圍架構，而不是傳統連續時間型快閃式類比數位轉換器。除此之外，我們還使用偏移消除、管線運作和插補等技巧。在佈局後的模擬顯示當輸入頻率接近Nyquist rate時，都還有 5.2 個有效位元。差分非線性誤差和積分非線性誤差都小於 0.3 最小位元。 所消耗的功率為 62 mW，每一次資料轉換消耗 1.38 pJ。

    For multi-band OFDM UWB, we propose two low-power high-speed analog-to-digital converters (ADCs). The first design is a 5-bit 1-Gsample/s flash ADC fabricated in TSMC 0.18-m 1P6M CMOS process. The measurement results show that the effective number of bits (ENOB) is 4 and power consumption is 60 mW with the sampling rate of 600 MHz. The second design is a 6-bit 1-Gsample/s ADC implemented in TSMC 0.13-m 1P8M CMOS process. Instead of continuous time flash ADC, we use two-step subranging structure. In addition, we employ offset cancellation, pipelining, and interpolation techniques. The post-layout simulation shows that ENOB is above 5.2 bits when the input frequency is up to Nyquist rate. The differential nonlinearity (DNL) and integral nonlinearity (INL) are smaller than 0.3 LSB (Least Significant Bit). The power consumption is 62 mW and figure-of-merit (FOM) 1.38 pJ/conversion-step.

    List of Figures vi List of Tables x Chapter 1 Introduction 1 1.1 MOTIVATION 1 1.2 THESIS ORGANIZATION 4 Chapter 2 Basics of Flash Analog-to-Digital Converter 5 2.1 REFERENCE LADDER 6 2.2 PREAMPLIFIER 11 2.3 LATCH 17 2.4 DIGITAL DECODER 18 Chapter 3 Design Problems of High-Speed Analog-to-Digital Converters 20 3.1 SAMPLING CLOCK JITTER 20 3.2 SIGNAL-DEPENDENT DELAY 23 3.3 OFFSET IN PREAMPLIFIERS AND COMPARATORS 28 3.3.1 Yield versus DNL 28 3.3.2 Yield versus INL 30 3.3.3 Resistive averaging network 32 3.3.3.1 Output Voltage and Gain 32 3.3.3.2 Effect of Mismatches: INL and DNL 37 3.3.3.3 Combining Averaging with a Reduced Number of Amplifiers 42 3.3.4 Offset cancellation techniques 43 3.4 KICKBACK NOISE 46 3.5 COMPARATOR METASTABILITY 47 3.5.1 ROM-Based Decoders 47 3.5.2 Logic-Based Decoders 53 Chapter 4 Implementation of a Flash Analog-to-Digital Converter 56 4.1 STRUCTURE OF DESIGNED FLASH ADC 56 4.2 PREAMPLIFIER 58 4.3 TRACK-AND-HOLD AMPLIFIER 63 4.4 COMPARATOR 65 4.5 DIGITAL BACKEND 70 4.6 SIMULATION RESULTS 73 4.7 EXPERIMENTAL RESULTS 76 Chapter 5 Implementation of a Subranging Analog-to-Digital Converter 82 5.1 STRUCTURE OF DESIGNED SUBRANGING ADC 82 5.2 COARSE ADC 85 5.3 FINE ADC 86 5.3.1 Offset cancellation 87 5.3.2 Pipelining 90 5.3.3 Interpolation 93 5.4 DIGITAL DECODER 95 5.4.1 Error correction circuit 95 5.4.2 Non-overlapping clock generator 96 5.4.3 Clock divider 97 5.5 TIMING 98 5.6 SIMULATION RESULTS 100 Chapter 6 Conclusion and Future Work 106 Bibliography 108

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