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研究生： 林聖雄
Lin, Sheng-Hsiung
論文名稱： 一個在殘值放大時將負載分離之具有管線式架構的逐漸趨近式類比數位轉換器
A Pipelined SAR ADC with Loading-Separating Technique for Residue Amplification
指導教授： 張順志
Chang, Soon-Jyh
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2012
畢業學年度： 100
語文別： 英文
論文頁數： 89
中文關鍵詞： 類比數位轉換器 、管線式 、逐漸趨近式類比數位轉換器 、具有管線式架構的逐漸趨近式類比數位轉換器
外文關鍵詞： ADC, pipelined, SAR ADC, pipelined SAR ADC
相關次數： 點閱：118  下載：25 
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    • 先進製程有利於元件的操作速度(頻寬)，因此，具有高度數位化特性以及低功率消耗的逐漸趨近式類比數位轉換器成為中低速、中高解析度應用的主流。另一方面，管線式類比數位轉換器適合高速、高解析度的應用，但是，傳統的管線式類比數位轉換器由數個運算放大器所組成，消耗大量的功率。近幾年來，一種結合逐漸趨近式類比數位轉換器以及管線式類比數位轉換器優點的混合型架構日益受到重視。本篇論文實現一個十二位元每秒取樣五千萬次具有管線式架構的逐漸趨近式類比數位轉換器。
    為了降低乘積數位類比轉換器的輸出負載，此論文提出一個將輸出負載分離至兩個放大時序的技巧；此外，還提出一個具有分離路徑放大的乘積數位類比轉換器用以提升運算放大器的增益以及頻寬。藉由提出的兩項技巧，運算放大器的設計困難度以及功率消耗都被降低了。這個設計使用台積電90奈米1P9M互補式金氧半製程來實現晶片，其核心電路的面積為590 × 450 (微米平方)。量測到的差動非線性以及積分非線性分別在0.62/-0.84 LSB與2.27/-1.67 LSB之間，在每秒五千萬次的取樣頻率之下，得到最大的訊號雜訊失真比為63.56分貝且有效位元頻寬為20百萬赫茲，由量測結果顯示在我們提出的兩項技巧幫助下，此類比數位轉換器消耗了2.17毫瓦特，每次資料轉換消耗的能量為44飛焦耳。

    The advanced process favors the operation speed (bandwidth) of the device. Thus, the low-to-medium speed and medium-to-high resolution successive approximation (SAR) analog-to-digital converters (ADCs) are becoming popular because their highly digital characteristic and low power consumption. On the other hand, the pipelined ADCs are suitable for high-speed and high-resolution applications. But a traditional pipelined ADC consumes much power because it consists of several operational amplifiers (op-amps). A hybrid architecture combines the advantages of SAR and pipelined ADCs attracts much attention in recent years. This thesis implements a 12-bit 50-MS/s pipelined SAR ADC.
    A loading-separating technique is proposed to separate the total loading of multiplying digital-to-analog converter (MDAC) into two amplifying phases. Thus the MDAC output loading is reduced. Furthermore, a split-path amplification MDAC is proposed to enhance the gain and bandwidth of the op-amp. The design difficulty and power consumption of the op-amp are reduced by the proposed two techniques. This work is fabricated in TSMC 90-nm 1P9M CMOS technology and occupies 590 × 450 (μm2) active area. The measured DNL and INL are within 0.62/-0.84 LSB and 2.27/-1.67 LSB, respectively. The peak SNDR is 63.56 dB and effective resolution bandwidth (ERBW) is 20 MHz at 50 MHz sampling rate. The measurement results indicate that this ADC consumes 2.17 mW with 44 fJ/conversion-step figure-of-merit (FoM) by the proposed two techniques.

    Abstract I Contents VI List of Figures IX List of Tables XIII Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Organization 4 Chapter 2 Introduction of Pipelined ADCs 6 2.1 Operation Principle 6 2.2 Basic Building Blocks in a Pipelined ADC 9 2.2.1 Front-End Sample and Hold (S/H) 9 2.2.2 Sub-ADC 12 2.2.3 Multiplying Digital-to-Analog Converter (MDAC) 16 2.3 Non-ideal Effects in Pipelined Stages 20 2.3.1 Comparator Offset 20 2.3.2 Non-idealities of MOS Switches 22 2.3.3 Finite Open-Loop DC Gain and Linear Settling Errors from Op-amp 24 2.3.4 Capacitor Mismatch 27 Chapter 3 Introduction of Successive Approximation (SAR) ADCs 29 3.1 Operation Principle and Basic Building Blocks in a SAR ADC 29 3.2 Performance Enhancement Techniques for SAR ADC 32 3.2.1 Asynchronous Processing Method 32 3.2.2 Energy-Efficient DAC Switching Procedure 33 3.2.3 Top Plate Sampling Technique 37 3.3 Review of Recently Reported Pipelined SAR ADCs 39 Chapter 4 A 12-bit 50-MS/s Pipelined SAR ADC 41 4.1 ADC Architecture and Proposed Loading-Separating Technique 41 4.2 Circuit Design and Implementation 46 4.2.1 Bootstrapped Switch 46 4.2.2 Pseudo-Differential Op-amp and MDAC 48 4.2.3 Common-Mode Stabilization Circuit 56 4.2.4 Bias Circuit 59 4.2.5 Dynamic Comparator and Offset Calibration 59 4.2.6 DAC Switching Methods for the 1st and 2nd Stage SAR ADCs 63 4.2.7 Control Circuit of Reference Switch 66 4.2.8 Digital Error Correction Circuit 68 4.3 Layout and Floor Plan 70 4.4 Simulation Results 72 4.5 Experimental Results 76 4.6 Summary 79 Chapter 5 Conclusion and Future Work 81 5.1 Conclusion 81 5.2 Future Work 82 Reference 83

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