| 研究生: |
劉佳協 Liu, Chia-Hsieh |
|---|---|
| 論文名稱: |
60-GHz毫米波CMOS射頻前端RFICs及關鍵被動元件之研究設計 Research on CMOS RFICs and Passive Key Components Design for 60-GHz Millimeter-Wave RF Front-End |
| 指導教授: |
莊惠如
Chuang, Huey-Ru |
| 學位類別: |
碩士 Master |
| 系所名稱: |
電機資訊學院 - 電腦與通信工程研究所 Institute of Computer & Communication Engineering |
| 論文出版年: | 2007 |
| 畢業學年度: | 95 |
| 語文別: | 中文 |
| 論文頁數: | 109 |
| 中文關鍵詞: | 毫米波 、緊縮微帶諧振單元 、源極退化電感 |
| 外文關鍵詞: | source degeneration inductor, Marchand balun, millimeter-wave, compact microstrip resonator cell |
| 相關次數: | 點閱:80 下載:8 |
| 分享至: |
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本論文主要針對毫米波CMOS RFICs射頻前端關鍵元件進行研究與製作,晶片製作使用國家晶片中心提供的標準TSMC CMOS 0.18 μm製程,內容分為兩個部份:
第一部份介紹毫米波的研究背景,毫米波具有良好的高速傳送特性,可應用於短距離無線傳輸。本論文根據參考文獻,介紹IEEE 802.15.3c之60 GHz毫米波射頻前端收發機系統規劃,針對包括靈敏度、SNR、通道頻寬、傳輸速率等進行討論,並提出60-GHz WPAN鏈路預算,希望對射頻系統規劃者與電路設計者有參考作用。
第二部份為毫米波CMOS RFICs射頻前端關鍵元件之設計與量測。平衡器採用Marchand balun架構搭配輸出匹配網路,利用晶片設計之多層式結構增加耦合量,並提出額外加入第四層金屬之屏蔽效應,有效改善平衡效果。量測結果在25–65 GHz內,振幅不平衡小於 ±1.5 dB,相位不平衡小於 ±10o,頻寬百分比為89 %。低雜訊放大器採用兩級串接架構之共源極放大器,在有限功率的考量下選擇電晶體尺寸,達成低功率設計,並使用Ansoft HFSS模擬所需之源極退化電感,所有傳輸走線均使用Sonnet模擬,由Agilent ADS進行共同模擬,務必要求佈局與模擬一致。量測頻率為20 GHz,當供應電壓Vdd為1.2 V時,整體的消耗功率為9.6 mW、增益為9.3 dB、雜訊指數為4.4 dB;當供應電壓Vdd為1.0 V時,整體的消耗功率為7.0 mW、增益為8.5 dB、雜訊指數為4.6 dB,未來可將設計頻率提升至毫米波頻段。帶通濾波器採用ACMRC結構進行設計,產生兩個零點頻率,搭配輸入與輸出端之耦合電容產生帶通效果,其中耦合電容亦使用多層式結構實現,總晶片面積為0.85 mm × 0.64 mm,ACMRC結構面積為0.45 mm × 0.27 mm。量測結果在61–68 GHz內,插入損失小於3.9 dB,低頻零點產生於51 GHz,高頻零點則產生於81.75 GHz,且截止區有不錯的衰減效果。
另外本論文包含兩個附錄,其中附錄A為60-GHz WPAN射頻前端系統文獻回顧,介紹兩篇已發表論文之系統研究;附錄B為57-64 GHz毫米波CMOS射頻接收機前端電路,使用國家晶片中心提供的標準TSMC CMOS 0.13 μm製程,主要介紹低雜訊放大器與帶通濾波器之共同模擬。
This thesis presents the research on CMOS RFICs and key components for millimeter-wave RF front-end. The RFICs are designed with TSMC 0.18 μm 1P6M standard CMOS fabrication process supplied by CIC.
In the first part, the properties of the millimeter-wave application for short-range high data-rate WPAN is introduced. System planning parameters for 60-GHz RF front-end including sensitivity, SNR, channel bandwidth and data-rate are derived to meet IEEE 802.15.3c standard requirements. The simple link budget of the 60-GHz WPAN system is shown.
The second part of this thesis is about the design and measurement of CMOS RFICs and key components. Marchand balun with an output matching network is designed. The fabricated CMOS balun uses multilayer coupling with the top two layers to enhance the coupling factor. A technique for achieving good balance with the fourth metal layer microstrip conductor is used in the designed balun. The measured amplitude imbalance is about ±1.5 dB with a corresponding phase difference about ±10o from 25 to 65 GHz , over the 89 % operating frequency band.
The two stage cascade common source LNA takes account of the low power issue to choose the size of the transistors. The source degeneration inductor and all traces are simulated by Ansoft HFSS and Sonnet. Agilent ADS is used to integrate the co-simulation design. Measurement results at 20 GHz:when supply voltage is 1.2 V, total power consumption is 9.6 mW, gain is 9.3 dB, noise figure is 4.4 dB; when supply voltage is 1.0 V, total power consumption is 7.0 mW, gain is 8.5 dB, noise figure is 4.6 dB. The ACMRC structure is used to design the filter with two avalible zero frequencies. The input and output capacitors using multilayer coupling are added to create the passband of the filter. The size of the chip is 0.85 mm 0.64 mm, and the size of the ACMRC structure is 0.45 mm × 0.27 mm. The measured insertion loss is less then 3.9 dB from 61 to 68 GHz. And the two zero frequencies are measured at 51 GHz and 81.75 GHz.
In addition, the paper survey of the 60-GHz WPAN system and the design of the 60-GHz RF front-end including antenna, filter and LNA are appendixed.
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