本論文分析一個零相移脈寬調變混疊失真抑制的D類放大器並對其作最佳化與驗證。在系統最佳化的部分，針對最佳化品質因數的部分，實現了切換頻率、功率輸出級大小以及運算放大器的增益、頻寬與電流消耗之最佳化。實現的零相移PWM混疊失真抑制技術利用兩個前饋路徑來解決先前技術相位偏移的問題並且克服頻帶外衰減能力與頻帶內增益的權衡。因此，在消除脈寬調變混疊失真時不會犧牲對頻帶內失真的抑制能力且實現之技術根據功率輸出級失真的考量可以達到最佳的切換頻率。與現存之脈寬調變混疊失真抑制之技術相比，實現之技術可在最佳的切換頻率達到好的總諧波失真加雜訊，因此能夠完成一個最佳的靜態電流設計。
此晶片實現於TSMC 0.5微米技術，經驗證後，在8歐姆之負載下，此技術改善總諧波失真加雜訊量為15dB，跟現有文獻相比，此晶片實現達到在P/N輸出級下有-98.01dB總諧波失真加雜訊量，並具有最佳之靜態電流517微安培與最高的品質因數1416，在N/N輸出級下有-97.29dB總諧波失真加雜訊量，並具有最佳之靜態電流337微安培與最高的品質因數2010。

In this thesis, an analysis for class-D amplifier with zero-phase-shift PWM-Aliasing-Distortion reduction technique is optimized and verified. System optimization about switching frequency, power-stage sizing and OPAMP’s gain, bandwidth, current consumption for optimized figure-of-merit is realized. The realized zero-phase-shift PWM-Aliasing-Distortion reduction technique utilizes two feedforward paths to solve phase-shift problem in previous work and overcome the trade-off between out-of-band loop attenuation and in-band loop gain. Therefore, the PWM-Aliasing-Distortion reduced without sacrificing high in-band distortion suppression capability and the realized technique can achieve at the optimized switching frequency with power-stage distortion consideration. Compared with existing PWM-Aliasing-Distortion reduction techniques, the realized technique achieves a good total harmonic distortion plus noise (THD+N) performance with the optimized switching frequency, resulting in the optimized quiescent current design.
Implemented in TSMC 0.5μm technology, the realized technique verified to improve the lowest THD+N by around 15dB with an 8-Ω load. Compared with state-of-the-arts, this work achieves -98.01dB THD+N (A-weighting) with the optimized quiescent current of 517μA and the highest figure-of-merit of 1416 for P/N power stage and -97.29dB THD+N (A-weighting) with the optimized quiescent current of 337μA and the highest figure-of-merit of 2010 for N/N power stage .

[1] K. H. Chen and Y. S. Hsu, “A high-PSRR reconfigurable class-AB/Daudio amplifier driving a hands-free/receiver 2-in-1 loudspeaker,”IEEE J. Solid-State Circuits, vol. 47, no. 11, pp. 2586–2603, Nov.2012.
[2] R. Becker and W. H. Groeneweg, “An audio amplifier providing up to 1 Watt in standard digital 90-nm CMOS,” IEEE J. Solid-State Circuits, vol. 41, no. 7, pp. 1648–1653, Jul. 2006.
[3] H. Ma, R. van der Zee, and B. Nauta, “Design and analysis of a high efficiency high-voltage class-D power output stage,” IEEE J. Solid-State Circuits, vol. 49, no. 7, pp. 1514–1524, Jul. 2014.
[4] L. Dooper and M. Berkhout, “A 3.4 W digital-in class-D audio amplifier in 0.14μm CMOS,” IEEE J. Solid-State Circuits, vol. 47, no. 7, pp. 1524–1534, Jul. 2012.
[5] L. Guo, T. Ge, and J. S. Chang, “A 101 dB PSRR, 0.0027% THD + N and 94% power-efficiency filterless class D amplifier,” IEEE J. Solid-State Circuits, vol. 49, no. 11, pp. 2608–2617, Nov. 2014.
[6] M. Wang, X. Jiang, J. Song, and T. L. Brooks, “A 120dB dynamic range 400mW Class-D speaker driver with fourth-order PWM modulator,” IEEE J. Solid-State Circuits, vol. 45, no. 8, pp. 1427–1435, Aug. 2010.
[7] M. A. Teplechuk, T. Gribben, and C. Amadi, “True filterless class-Daudio amplifier,” IEEE J. Solid-State Circuits, vol. 46, no. 12, pp. 2784–2793, Dec.2011.
[8] T.-H.Kuo, S.-H.Chien, J.-J. Huang, Y.-W. Chen and Y.-A. Lee, "A 2.4 mA Quiescent Current, 1 W Output Power Class-D Audio Amplifier With Feed-Forward PWM-Intermodulated-Distortion Reduction," in IEEE J. Solid-State Circuits, vol. 51, no.6, pp. 1436-1445, June 2016.
[9] S.-H.Chien, Y.-W. Chen and T.-H.Kuo, "A 0.96mA Quiescent Current, 0.0032% THD+N, 1.45W Class-D Audio Amplifier with Area-Efficient PWM-Residual-Aliasing Reduction," in ISSCC Dig. Tech. Papers, pp. 60-61, Feb 2018.
[10] S.-H.Chien, and T.-H.Kuo et al., "A class-D Audio Amplifier with Zero-Phase-Shift PWM-Aliasing-Distortion Reduction," private communication and will be submitted to IEEE J. Solid-State Circuits.
[11] 陳翊文(民105)。具脈寬調變互調失真抑制之低靜態電流高傳真D類音頻放大器 (未出版之碩士論文)。國立成功大學，台南市。
[12] M. Berkhout, "An integrated 200-W class-D audio amplifier," in IEEE J. Solid-State Circuits, vol. 38, no.7, pp. 1198-1206, July 2003.
[13] I.D.Mosely, P.H. Mellor, and C. M. Bingham, "Effect of dead time on harmonic distortion in class-D audio power amplifiers," in Electron. Lett., vol.35,no.12, pp. 950-952, June 1999.
[14] J.-M.Liu, S.-H.Chien, and T.-H.Kuo, "A 100W 5.1-channel digital class-D audio amplifier with single-chip design," in IEEE J. Solid-State Circuits, vol.47 no.6, pp. 1344-1354, 2012.
[15] M. A. Teplechuk, T. Gribben, and C. Amadi, "Filterless integrated Class-D audio amplifier achieving 0.0012% and 96 dB PSRR when supplying 1.2W," in ISSCC Dig. Tech. Papers, pp. 240-241, Feb 2011.
[16] R. Scherier et al, Understanding Delta-Sigma Data Converters, IEEE-Press, Wiley-InterScience, 2005.
[17] W. -C Wang, Y.-H Lin, "A 118dB-PSRR 0.00067%(-103.5dB) THD+N and 3.1W fully differential class-D audio amplifier with PWM common-mode control," ISSCC Dig. Tech. Papers, pp. 90-91, Feb 2016.
[18] M. Kinyua, R. Wang and E. Soenen, "Integrated 105 dB SNR, 0.0031% THD+N Class-D Audio Amplifier With Global Feedback and Digital Control in 55 nm CMOS," IEEE J. Solid-State Circuits, vol. 50, no.8, pp. 1764-1771, Aug 2015.
[19] X. Jiang, J. Song, D. Cheung, M. Wang, and S. Arunachalam, "Integrated Class-D audio amplifier with 95% efficiency and 105 dB SNR," IEEE J. Solid-State Circuits, vol. 49, no. 11, pp. 2387-2396, Nov 2014.
[20] A. I. Colli-Menchi, J. Torres and E. Sánchez-Sinencio, "A Feed-Forward Power-Supply Noise Cancellation Technique for Single-Ended Class-D Audio Amplifiers," IEEE J. Solid-State Circuits, vol. 49, no. 3, pp. 718-728, Mar 2014.
[21] J. Torres, A. Colli-Menchi, M. A. Rojas-Gonzalez and E. Sanchez-Sinencio, "A Low-Power High-PSRR Clock-Free Current-Controlled Class-D Audio Amplifier," IEEE J. Solid-State Circuits, vol. 46, no. 7, pp. 1553-1561, July 2011.
[22] W. -C Wang, Y.-H Lin, "A 0.0004% (-108dB) THD+N, 112dB-SNR, 3.15W Fully Differential Class-D Audio Amplifier with Gm Noise Cancellation and Negative Output-Common-Mode Injection Techniques," ISSCC Dig. Tech. Papers, pp. 58-59, Feb 2018.