使用運行/停止/恢復這種除錯方法對多重時脈電路進行除錯時，必須要對資料無效化問題進行處理。當資料無效化問題發生時，意謂接收時脈域中的正反器抓取到不正確的資料，因而使得待除錯電路無法正確地恢復其動作。另一方面，除錯解析度指的是可以被停止的週期數佔待除錯電路正常運行時所需週期數的比例，這個比例應該被最佳化以提昇除錯效率。本論文提出了一個結合軟體程式與硬體電路設計的機制來處理這些問題。軟體程式會根據使用者所設定的中斷點計算出一個觸發停止訊號的週期。硬體設計主要是一個時脈控制器，用來將停止訊號轉換成適當的中斷訊號來通知待除錯時脈域。藉由如此，我們能夠根除資料無效化問題，並且允許待除錯電路中的時脈訊號在幾乎每一個時脈週期被停止。在現場可程式化邏輯閘陣列開發板上的實驗結果顯示了本論文提出的除錯機制是可行並且有效的。

Data invalidation is a problem that needs to be addressed when debugging a multiple-clock design with the run-stop-resume (RSR) debug methodology. The problem occurs when flip-flops in a receiving clock domain capture incorrect data during debugging, and thus the circuit under debug (CUD) cannot be resumed correctly. On the other hand, debug resolution refers to the ratio of clock frequencies that can be stopped over all normal clock cycles. This ratio should be optimized to enhance debug efficiency. In this thesis, we propose a novel mechanism that combines software programs and hardware designs to deal with these problems. The software is developed to calculate the exact time to activate a stop signal based on the user-defined breakpoint. The hardware is mainly a clock controller that converts the stop signal to the appropriate gating signals for all the clock domains under debugging. By doing this, we can totally eliminate data invalidation as well as allow users to stop the CUD at almost any clock cycle. Experimental results on a field programmable gate array (FPGA) prototyping board validate the effectiveness and efficiency of the proposed debug mechanism.

[1] R. Ginosar, “Metastability and Synchronizers: A Tutorial,” IEEE Design & Test of Computers, pp. 23-35, Sept.-Oct. 2011.
[2] A.B.T. Hopkins and K.D. McDonald-Maier, “Debug Support for Complex Systems On-Chip: a Review,“ IEEE Proceedings - Computers and Digital Techniques, pp. 197-207, July 2006.
[3] B. Vermeulen and S.K. Goel, “Design for Debug: Catching Design Errors in Digital Chips,“ IEEE Design & Test of Computers, pp. 35-43, May-June 2002.
[4] B. Vermeulen, “Functional Debug Techniques for Embedded Systems,” IEEE Design & Test of Computers, pp. 208-215, May-June 2008.
[5] C. Dike, and E. Burton, “Miller and Noise Effects in a Synchronizing Flip-Flop,” IEEE Solid-State Circuits, pp. 849-855, June 1999.
[6] R.W. Apperson, Zhiyi Yu, M.J. Meeuwsen, T. Mohsenin, and B.M. Baas, “A Scalable Dual-Clock FIFO for Data Transfers Between Arbitrary and Haltable Clock Domains,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp. 1125-1134, Oct. 2007.
[7] Chia-Chih Yen, Ten Lin, H. Lin, Kai Yang, Tayung Liu, and Yu-Chin Hsu, “A General Failure Candidate Ranking Framework for Silicon Debug,” IEEE VLSI Test Symposium (VTS), pp. 352-358, Apr. 2008.
[8] Sung-Boem Park and S. Mitra, “IFRA: Instruction Footprint Recording and Analysis for Post-Silicon Bug Localization in Processors," IEEE Design Automation Conference (DAC), pp. 373-378, June 2008.
[9] S.K. Goel and B. Vermeulen, “Hierarchical Data Invalidation Analysis for Run-stop Debug on Multiple-Clock System Chips,“ In Proceedings IEEE International Test Conference (ITC), pp. 1103-1110, 2002.
[10] R. Ginosar, “Fourteen Ways to Fool Your Synchronizer,” In Proceedings of the Ninth International Symposium on Asynchronous Circuits and Systems (ASYNC), pp. 89-96, May 2003.
[11] I.W. Jones, S. Yang, and M. Greenstreet, “Synchronizer Behavior and Analysis,” IEEE Symposium on Asynchronous Circuits and Systems (ASYNC), pp. 117-126, May 2009.
[12] J.-M. Chabloz and A. Hemani, “A Flexible Communication Scheme for Rationally-Related Clock Frequencies,” In Proceedings IEEE International Conference on Computer Design (ICCD), pp. 109-116, Oct. 2009.
[13] S. Balasubramanian, N. Natarajan, O. Franza, and C. Gianos, “Deterministic Low-Latency Data Transfer across Non-Integral Ratio Clock Domains,” In Proceedings the International Conference on VLSI Design (VLSID), pp. 1063-1067, Jan. 2006.
[14] J.-L. Gao, Y.-H. Han, and X.-W. Li, “Eliminating Data Invalidation in Debugging Multiple-Clock Chips,” In Proceedings Design, Automation and Test in Europe Conference (DATE), pp. 1-6, March 2011.
[15] Chi-Hung Yao and Kuen-Jong Lee, “A Low-Cost On-Chip SOC Debug Platform with Multiple Clock Domain Breakpoint Insertion Capabilities,” Master Thesis, Dept. of E.E., NCKU, Taiwan, 2009.
[16] Shih-Hsing Hsieh and Kuen-Jong Lee, “A SoC Debug Platform with Inside-Core Adjustment and Event Trigger Capabilities,” Master Thesis, Dept. of E.E., NCKU, Taiwan, 2009.
[17] S. Verma and A.S. Dabare, “Understanding Clock Domain Crossing Issues,” EE Times, Dec. 24, 2007; http://www.gstitt.ece.ufl.edu/courses/eel4712/lectures/metastability/EEIOL_2007DEC24_EDA_TA_01.pdf.