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研究生： 夏翊瑄
Hsia, Yi-Hsuan
論文名稱： 具有N路濾波之解調器的超低功耗FSK/OOK喚醒接收器
An Ultra-Low-Power FSK/OOK Wake-Up Receiver Featuring N-Path Filter Based Demodulator
指導教授： 鄭光偉
Cheng, Kuang-Wei
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2024
畢業學年度： 112
語文別： 英文
論文頁數： 126
中文關鍵詞： 低功率 、喚醒接收機 、開關鍵控 、頻率鍵移 、多路徑技術 、轉導電容頻率偏移
外文關鍵詞： low-power, WuRx, OOK, FSK, N-path technique, gm-C frequency shifting
相關次數： 點閱：43  下載：15 
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    • 隨著無線感測器網路和物聯網應用的需求不斷增加，對於各個感測節點的要求也越來越嚴刻。能夠在維持高靈敏度的條件下做到低功耗以延長電池的使用時長以及盡可能縮小尺寸以降低成本的接收器成了主要追求的目標。
    本篇論文提出應用於433百萬赫茲可做開關鍵控及頻率鍵移訊號之解調的低功耗喚醒接收器。其中首級低雜訊放大器與混頻器採用電流再利用的架構以降低功耗，此外混頻器的部分還選用次諧波混頻器，將低了本地振盪器所需要提供的頻率以減輕其負擔。而在解調器的部分採用具有增益的多路徑濾波/混頻器，除了能夠取代高品質因數的外部元件以降低面積以外，還能提升整體增益，再搭配轉導電容頻率偏移的技術，讓頻率使用更富彈性。本晶片使用90奈米互補式金屬氧化物半導體製程製造，工作於433百萬赫茲、資料傳輸率為每秒100千位元，預期能達到−100 dBm的靈敏度，此晶片操作在1伏特工作電壓下，消耗183微瓦。

    With the increasing demand for wireless sensor networks and IoT applications, the requirements for individual sensor nodes have become more stringent. The receiver achieving low power consumption to extend battery life and minimize size to reduce costs while maintaining high sensitivity has become the primary goal.
    This thesis proposes a low-power wake-up receiver for demodulating on-off keying (OOK) and frequency shift keying (FSK) signals at 433 MHz. The first-stage low-noise amplifier and mixer adopt a current-reuse architecture to reduce power consumption. Additionally, the mixer utilizes a sub-harmonic architecture to reduce the required frequency of the local oscillator, thereby lightening its load. The demodulator employs a gain-enhanced N-path filter/mixer, replacing high-quality external components to reduce area and improve overall gain. Coupled with transconductance-capacitance frequency shifting techniques, it enhances frequency flexibility. This chip is fabricated using a 90-nm CMOS process, operating at 433 MHz with a data rate of 100 kbps. It is expected to achieve a sensitivity of -100 dBm, operating at 1 V with a power consumption of 183 μW.

    1. Introduction 14 1.1. Motivation 14 1.2. Thesis Organization 16 2. Fundamental Architecture Review 17 2.1 Control Method in sensor nodes 17 2.1.1. Duty-Cycle Control in Sensor Nodes 17 2.1.2. Always-On Wake-Up Receiver 19 2.2 Wake-Up Receiver Target specifications 20 (A) Area 20 (B) Cost 20 (C) Sensitivity 21 (D) Power consumption 21 (E) Energy-per-bit ratio 21 2.3 State-of-The-Art Wake-up Receivers 25 2.3.1. Envelope Detection Architecture 25 2.3.2. Tuned-RF Architecture 26 2.3.3. Uncertain-IF Architecture 28 2.3.4. N-Path Filter Based Architecture 30 2.4 State-of-The-Art demodulator 33 (A) Coherent demodulation 33 (B) Non-coherent demodulation 33 2.4.1 OOK demodulator 33 2.4.2 FSK demodulator 34 2.5 Conclusions 37 3. Proposed N-Path Filter Based WuRx 38 3.1. WuRx Architecture 39 3.1.1. Frequency Plan 42 3.2. N-Path Filter/Mixer 44 3.2.1. 4-Path Passive Filter 44 3.2.2. Gain Enhanced N-Path Filter/Mixer 51 3.2.3. gm-C Frequency Shift Technique 55 3.3. RF Front-End Circuits 61 3.3.1. CG LNA with Current-Reuse Sub-harmonic Mixer 61 3.3.2. Local Oscillator and Clock Generator 68 3.4. IF-band and Baseband Circuit 76 3.4.1. Variable gain amplifier 76 3.4.2. Baseband block 81 4. Simulation and Measurement of Whole System 92 4.1. Simulation of Whole System 92 4.2. Measurement of test chip 98 4.2.1. Layout Implementation 98 4.2.2. Measurement Setup 99 4.2.1. Measurement Result 101 4.3. Measurement of WuRx 103 4.3.1. Layout Implementation 103 4.3.2. Measurement Setup 104 4.3.3. Measurement Result 107 5. Conclusions and Future Works 118 5.1. Conclusions 118 5.2. Future Work 119 5.2.1 Gm-C Frequency Shift Technique 119 5.2.2 Comparator Clock 119 5.2.3 FSK Demodulator 121 Bibliography 122

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