由於系統單晶片(System-on-a-Chip; SOC)技術發展愈來愈成熟，雙核心處理器(Dual Core Processor)如ARM與DSP，運用在手機、個人數位產品、數位照相機及消費電子上愈來愈普及，故嵌入式數位訊號處理器在SoC系統上，扮演的角色愈來愈重要。從測試的觀點而言，傳統以掃瞄鏈(Scan Chain)為基礎的測試架構，將會造成硬體電路與測試成本的增加，甚至降低整體電路之效能，因此如何在不增加面積與不降低性能的前提下，有效率去測試數位訊號處理器，進而提升錯誤涵蓋率，是一個非常重要的研究主題。
本篇論文主要包含兩大部份：第一個部份是針對相容於TMS320C54x系列的數位訊號處理器架構之設計，我們透過Easy-Platform來驗證所設計之數位訊號處理器(NCKU DSP)的功能是否正確。NCKU DSP處理器的指令集完全相容於TI TMS320C54x。第二個部份為使用軟體功能測試方法針對所設計出來的數位訊號處理器作測試。主要方法之一利用有條件限制之自動樣本產生器(Constrained ATPG)，針對子模組來產生測試樣本，並透過載入指令(Load Instruction)將測試樣本引進到子模組，再透過儲存指令(Store Instruction)將錯誤效應(fault effect)傳遞(propagation)到輸出腳，使用這個方法具有較小的測試程式，可重複使用測試範本，不需要額外的電路和不降低電路效能的優點。

With rapid development of SoC (System-on-Chip) techniques, dual core processors (ARM and DSP processor) are extensively used in consumer electronics like mobile phone, digital camera, etc. Since the embedded processor plays an important role in SoC, an efficient test method with little overhead and high fault coverage has become a critical issue. Traditionally the CUT (circuit under test) is inserted scan chains to improve fault coverage; however the tradeoff is the area overhead and performance degradation.
This work first presents a DSP processor designs named NCKU DSP based on TMS320C54x series, which is verified on EASY-Platform. ISA (instruction set architecture) of NCKU DSP processors is compatible with that of TI TMS320C54x. Then we propose a software-based test method for the developed NCKU DSP. The ATPG (Auto Test Pattern Generator) is constrained to ensure that the test pattern can be loaded into sub-module under test and the test response can be transmitted out of DSP by the store instruction; thus a smaller test program size can be obtained and test patterns can also be reused. Additionally, since the test program is developed based on existing instruction sets of DSP processor, there is no area overhead and performance degradation.

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